C8051F530A-IT from SILICON LABS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P0.2	bidirectional	Port 0.2, digital I/O or analog input.
2	P0.1	bidirectional	Port 0.1, digital I/O or analog input.
3	RST/C2CK	bidirectional	Device reset (open-drain output of internal POR or VDD monitor, driven low externally to force a system reset; 1 kΩ pullup to VREGIN recommended) and clock signal for the C2 debug interface.
4	P0.0/VREF	bidirectional	Port 0.0, digital I/O or analog input, also external VREF input.
5	GND	power_in	Ground.
6	VDD	power_in	Core supply voltage.
7	VREGIN	power_in	On-chip voltage regulator input.
8	P1.7	bidirectional	Port 1.7, digital I/O or analog input.
9	P1.6	bidirectional	Port 1.6, digital I/O or analog input.
10	P1.5	bidirectional	Port 1.5, digital I/O or analog input.
11	P1.4	bidirectional	Port 1.4, digital I/O or analog input.
12	P1.3	bidirectional	Port 1.3, digital I/O or analog input.
13	P1.2/CNVSTR	bidirectional	Port 1.2, digital I/O or analog input, also external ADC0 convert-start input.
14	P1.1	bidirectional	Port 1.1, digital I/O or analog input.
15	P1.0/XTAL2	bidirectional	Port 1.0, digital I/O or analog input, also external clock output (crystal/resonator excitation driver) or external clock input for CMOS, capacitor or RC oscillator configurations.
16	P0.7/XTAL1	bidirectional	Port 0.7, digital I/O or analog input, also external oscillator return for a crystal or resonator.
17	P0.6/C2D	bidirectional	Port 0.6, digital I/O or analog input, also bi-directional data signal for the C2 debug interface.
18	P0.5/RX	bidirectional	Port 0.5, digital I/O or analog input, with UART RX function on this 'F53xA variant.
19	P0.4/TX	bidirectional	Port 0.4, digital I/O or analog input, with UART TX function on this 'F53xA variant.
20	P0.3	bidirectional	Port 0.3, digital I/O or analog input.

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	TSSOP-20
Category	Embedded Processors & Controllers
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ambient temperature under bias		-55		135	°C		25
Storage temperature		-65		150	°C		25
Voltage on VREGIN with respect to GND	VREGIN	-0.3		5.5	V		25
Voltage on VDD with respect to GND	VDD	-0.3		2.8	V		25
Maximum output current sunk by any port pin				100	mA		25
Maximum output current sourced by any port pin				100	mA		25
Maximum total current through VREGIN and GND				500	mA		25
Supply input voltage	VREGIN	1.8		5.25	V	Output current < 1 mA, C8051F52xA/53xA	26
Digital supply voltage	VDD	1.8		2.7	V	C8051F52xA/53xA	26
System clock	SYSCLK	0		25	MHz		26
Specified operating temperature range		-40		125	°C		26
Digital supply current, CPU active	IDD		5.1	9	mA	VDD = 2.1 V, Clock = 25 MHz	26
Digital supply current, CPU active	IDD		7.3	13	mA	VDD = 2.6 V, Clock = 25 MHz	26
Digital supply current, CPU inactive (Idle)	Idle IDD		2.2	5	mA	VDD = 2.1 V, Clock = 25 MHz	27
Digital supply current, CPU inactive (Idle)	Idle IDD		3	6.5	mA	VDD = 2.6 V, Clock = 25 MHz	27
Core supply RAM data retention voltage			1.5		V		26
Digital supply current (Stop or Suspend)			2		µA	Oscillator not running, VDD Monitor Disabled, T = 25 °C	27
Digital supply current (Stop or Suspend)			50		µA	Oscillator not running, VDD Monitor Disabled, T = 125 °C	27
ADC integral nonlinearity	INL	-3		3	LSB		28
ADC differential nonlinearity	DNL	-1		1	LSB	Guaranteed Monotonic	28
ADC offset error		-10	1	10	LSB		28
ADC full scale error		-20	1	20	LSB		28
ADC signal-to-noise plus distortion		60	66		dB	10 kHz sine-wave, single-ended input, 0 to 1 dB below full scale, 200 ksps	28
ADC SAR conversion clock				3	MHz		28
ADC burst mode oscillator				27	MHz		28
ADC track/hold acquisition time		1			µs		28
ADC throughput rate				200	ksps		28
ADC power supply current (from VDD)			1050	1400	µA	Operating Mode, 200 ksps	28
Internal reference output voltage		1.45	1.5	1.55	V	25 °C ambient (REFLV = 0)	29
Internal reference output voltage		2.15	2.2	2.25	V	25 °C ambient (REFLV = 1), VDD = 2.6 V	29
VREF temperature coefficient			33		ppm/°C		29
Voltage regulator input voltage range	VREGIN	2.2		5.25	V	C8051F52xA/53xA, VDD connected to VREGIN	30
Voltage regulator input voltage range	VREGIN	1.8		2.7	V	C8051F52xA/53xA, VDD not connected to VREGIN	30
Regulator output voltage	VDD	2	2.1	2.25	V	Output Current = 1 to 50 mA, REG0MD = 0	30
Regulator output voltage	VDD	2.5	2.6	2.75	V	Output Current = 1 to 50 mA, REG0MD = 1	30
Regulator bias current			1	5	µA	2.1 V operation (REG0MD = 0; T = 25 °C)	30
Comparator input offset voltage		-15		15	mV		31
Comparator input voltage range		-0.25			V	Inverting or Non-Inverting Input; max printed as VDD + 0.25	31
Comparator supply current at DC, Mode 0			6	30	µA	Mode 0	31
Comparator positive hysteresis 4		13	20	40	mV	CP0HYP1-0 = 11	31
RST output low voltage				0.8	V	IOL = 8.5 mA, VDD = 2.1 V	32
Missing clock detector timeout		100	350	650	µs	Time from last system clock rising edge to reset initiation	32
Reset time delay	TPORDelay			350	µs	Delay between release of any reset source and code execution at location 0x0000	32
Minimum RST low time to generate a system reset		10			µs		32
VDD monitor low threshold	VRST-LOW	1.65	1.75	1.8	V	C8051F52xA/53xA	32
VDD monitor high threshold	VRST-HIGH	2.25	2.3	2.4	V	C8051F52xA/53xA	32
VDD monitor supply current			1	2	µA	VDD = 2.1 V	32
Flash size		7680			bytes	'F530/0A/1/1A	33
Flash erase cycle time		27	32	38	ms		33
Flash write cycle time		57	65	74	µs		33
Port I/O output low voltage	VOL			45	mV	VREGIN = 2.7 V: IOL = 70 µA	33
Port I/O output low voltage	VOL			550	mV	VREGIN = 2.7 V: IOL = 8.5 mA	33
Port I/O output low voltage	VOL			40	mV	VREGIN = 5.25 V: IOL = 70 µA	33
Port I/O output low voltage	VOL			400	mV	VREGIN = 5.25 V: IOL = 8.5 mA	33
Internal oscillator frequency			24.53		MHz	IFCN = 111b	34
Internal oscillator supply current (from VDD)			800	1100	µA	Oscillator On, OSCICN[7:6] = 11b	34
Internal oscillator temperature sensitivity TC1	TC1		5		ppm/°C	Constant Supply	34

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		8. The recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body Components.	44

CAD (KiCad official)

Symbol: C8051F530A-IT
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: c8051f530a-it-etched.step / c8051f530a-it-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f530a-it.step / c8051f530a-it.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (220 pp, sha256 8675c7e56bd30f64, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

C8051F530A-IT

Verified C8051F530A-IT

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3D Model

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Schematic Symbol

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