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C8051F506-IQR

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SILICON LABS Pre-ordered MCUs, LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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C8051F506-IQR

SILICON LABS · Pre-ordered MCUs · LQFP-32(7x7)

C8051F506-IQR from SILICON LABS, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Port 0.1, digital I/O or analog input.
2 VIO power_in Port I/O supply voltage; must be connected.
3 VREGIN power_in Voltage regulator input.
4 VDD power_in Digital supply voltage; must be connected.
5 VDDA power_in Analog supply voltage; must be connected.
6 GND power_in Digital ground; must be connected.
7 GNDA power_in Analog ground; must be connected.
8 P0.0 bidirectional Port 0.0, digital I/O or analog input.
9 P3.0/C2D bidirectional Port 3.0 digital I/O or analog input, shared with the bi-directional data signal for the C2 debug interface.
10 RST/C2CK bidirectional Device reset, open-drain output of internal POR or VDD monitor that an external source can drive low to reset the system, shared with the clock signal for the C2 debug interface.
11 P2.7 bidirectional Port 2.7, digital I/O or analog input.
12 P2.6 bidirectional Port 2.6, digital I/O or analog input.
13 P2.5 bidirectional Port 2.5, digital I/O or analog input.
14 P2.4 bidirectional Port 2.4, digital I/O or analog input.
15 P2.3 bidirectional Port 2.3, digital I/O or analog input.
16 P2.2 bidirectional Port 2.2, digital I/O or analog input.
17 P2.1 bidirectional Port 2.1, digital I/O or analog input.
18 P2.0 bidirectional Port 2.0, digital I/O or analog input.
19 P1.7 bidirectional Port 1.7, digital I/O or analog input.
20 P1.6 bidirectional Port 1.6, digital I/O or analog input.
21 P1.5 bidirectional Port 1.5, digital I/O or analog input.
22 P1.4 bidirectional Port 1.4, digital I/O or analog input.
23 P1.3 bidirectional Port 1.3, digital I/O or analog input.
24 P1.2 bidirectional Port 1.2, digital I/O or analog input.
25 P1.1 bidirectional Port 1.1, digital I/O or analog input.
26 P1.0 bidirectional Port 1.0, digital I/O or analog input.
27 P0.7 bidirectional Port 0.7, digital I/O or analog input.
28 P0.6 bidirectional Port 0.6, digital I/O or analog input.
29 P0.5 bidirectional Port 0.5, digital I/O or analog input.
30 P0.4 bidirectional Port 0.4, digital I/O or analog input.
31 P0.3 bidirectional Port 0.3, digital I/O or analog input.
32 P0.2 bidirectional Port 0.2, digital I/O or analog input.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Temperature under Bias -55 135 °C 42
Storage Temperature -65 150 °C 42
Voltage on VREGIN with respect to GND VREGIN -0.3 5.5 V 42
Voltage on VDD with respect to GND VDD -0.3 2.8 V 42
Voltage on VDDA with respect to GND VDDA -0.3 2.8 V 42
Voltage on VIO with respect to GND VIO -0.3 5.5 V 42
Maximum Total Current through VREGIN or GND 500 mA 42
Maximum Output Current Sunk by RST or any Port Pin 100 mA 42
Maximum Output Current Sourced by any Port Pin 100 mA 42
Supply Input Voltage VREGIN 1.8 5.25 V 43
Digital Supply Voltage, System Clock > 25 MHz VDD 2 2.75 V System Clock > 25 MHz 43
Digital Supply Voltage, System Clock < 25 MHz VDD 1 2.75 V System Clock < 25 MHz; min printed as VRST (Table 5.4) with footnote 1 43
Digital Supply RAM Data Retention Voltage 1.5 V 43
Port I/O Supply Voltage VIO 1.8 5.25 V Normal Operation 43
SYSCLK (System Clock) SYSCLK 0 50 MHz 43
SYSCLK High Time TSYSH 9 ns 43
SYSCLK Low Time TSYSL 9 ns 43
Specified Operating Temperature Range -40 125 °C 43
Digital Supply Current, CPU active IDD 10 11 mA VDD = 2.1 V, F = 25 MHz 43
Digital Supply Current, CPU active IDD 19 21 mA VDD = 2.1 V, F = 50 MHz 43
Digital Supply Current, CPU active IDD 14 21 mA VDD = 2.6 V, F = 25 MHz 44
Digital Supply Current, CPU active IDD 25 33 mA VDD = 2.6 V, F = 50 MHz 44
Digital Supply Current, CPU inactive (Idle) IDD 7.2 8 mA VDD = 2.1 V, F = 25 MHz 45
Digital Supply Current, CPU inactive (Idle) IDD 14 16 mA VDD = 2.1 V, F = 50 MHz 45
Digital Supply Current, CPU inactive (Idle) IDD 9.3 15 mA VDD = 2.6 V, F = 25 MHz 45
Digital Supply Current, CPU inactive (Idle) IDD 19 25 mA VDD = 2.6 V, F = 50 MHz 45
Digital Supply Current (Stop or Suspend) IDD 2 μA Oscillator not running, VDD Monitor Disabled, Temp = 25 °C 45
Output Low Voltage VOL 750 mV VIO = 1.8 V: IOL = 8.5 mA 47
RST Output Low Voltage 40 mV VIO = 5 V; IOL = 70 μA 48
RST Input Pullup Current 47 115 μA RST = 0.0 V, VIO = 5 V 48
VDD RST Threshold (VRST-LOW) VRST-LOW 1.65 1.75 1.8 V 48
VDD RST Threshold (VRST-HIGH) VRST-HIGH 2.25 2.3 2.45 V 48
Missing Clock Detector Timeout 200 370 600 μs VDD = 2.1V 48
Reset Time Delay 130 160 μs 48
Minimum RST Low Time to Generate a System Reset 6 μs 48
VDD Monitor Supply Current 1 2 μA 48
Flash Size (C8051F504/5/6/7-F510/1) 32768 Bytes 48
Flash Retention 10 Years 85 °C 48
Flash Erase Cycle Time 28 30 45 ms 25 MHz System Clock 48
Flash Write Cycle Time 79 84 125 μs 25 MHz System Clock 48
Internal Oscillator Supply Current 830 1300 μA Internal Oscillator On, OSCICN[7:6] = 11b 49
Oscillator Temperature Sensitivity TC1 TC1 5 ppm/°C Constant Supply 49
Clock Multiplier Input Frequency Fcmin 2 MHz 50
Clock Multiplier Output Frequency 50 MHz 50
Regulator Input Voltage Range VREGIN 1.8 5.25 V 50
Regulator Output Voltage VDD 2 2.1 2.25 V 2.1 V operation (REG0MD = 0) 50
Regulator Output Voltage VDD 2.5 2.6 2.75 V 2.6 V operation (REG0MD = 1) 50
Regulator Bias Current 1 9 μA 50
ADC Integral Nonlinearity INL 0.5 3 LSB typ and max printed as ± 51
ADC Differential Nonlinearity DNL 0.5 1 LSB Guaranteed Monotonic; typ and max printed as ± 51
ADC Offset Error -10 -1.8 10 LSB 51
ADC Full Scale Error -20 1.7 20 LSB 51
ADC Power Supply Current 1100 1500 μA Operating Mode, 200 ksps 51
Internal Reference Output Voltage 1.45 1.5 1.55 V 25 °C ambient (REFLV = 0) 52
Comparator Input Offset Voltage -10 10 mV 53
Comparator Supply Current at DC, Mode 0 6.2 20 μA Mode 0 53

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body 32

CAD (KiCad official)

  • Symbol: C8051F506-IQR
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: c8051f506-iqr-etched.step / c8051f506-iqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f506-iqr.step / c8051f506-iqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (314 pp, sha256 ab1c6f9eff92046e, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF