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C8051F500-IQR

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SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), QFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F500-IQR

SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · QFP-48(7x7)

C8051F500-IQR from SKYWORKS SILICON LABS, in a QFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Port 0.1 digital I/O or analog input, configured per PnMDIN, with the pin assigned by the Crossbar.
2 VIO power_in Port I/O supply voltage. Must be connected.
3 VREGIN power_in Voltage regulator input.
4 VDD power_in Digital supply voltage. Must be connected.
5 VDDA power_in Analog supply voltage. Must be connected.
6 GND power_in Digital ground. Must be connected.
7 GNDA power_in Analog ground. Must be connected.
8 P0.0 bidirectional Port 0.0 digital I/O or analog input; see SFR Definition 20.12 for configuration.
9 P4.7 bidirectional Port 4.7 digital I/O.
10 P4.6 bidirectional Port 4.6 digital I/O.
11 C2D bidirectional Bi-directional data signal for the C2 Debug Interface.
12 RST/C2CK bidirectional Device reset: open-drain output of the internal POR or VDD Monitor, and an external source can initiate a system reset by driving this pin low; the same pin carries the clock signal for the C2 Debug Interface.
13 P4.5 bidirectional Port 4.5 digital I/O.
14 P4.4 bidirectional Port 4.4 digital I/O.
15 P4.3 bidirectional Port 4.3 digital I/O.
16 P4.2 bidirectional Port 4.2 digital I/O.
17 P4.1 bidirectional Port 4.1 digital I/O.
18 P4.0 bidirectional Port 4.0 digital I/O; see SFR Definition 20.28 for a description.
19 P3.7 bidirectional Port 3.7 digital I/O.
20 P3.6 bidirectional Port 3.6 digital I/O or analog input.
21 P3.5 bidirectional Port 3.5 digital I/O or analog input.
22 P3.4 bidirectional Port 3.4 digital I/O or analog input.
23 P3.3 bidirectional Port 3.3 digital I/O or analog input.
24 P3.2 bidirectional Port 3.2 digital I/O or analog input.
25 P3.1 bidirectional Port 3.1 digital I/O or analog input.
26 P3.0 bidirectional Port 3.0 digital I/O or analog input; see SFR Definition 20.24 for a description.
27 P2.7 bidirectional Port 2.7 digital I/O or analog input.
28 P2.6 bidirectional Port 2.6 digital I/O or analog input.
29 P2.5 bidirectional Port 2.5 digital I/O or analog input.
30 P2.4 bidirectional Port 2.4 digital I/O or analog input.
31 P2.3 bidirectional Port 2.3 digital I/O or analog input.
32 P2.2 bidirectional Port 2.2 digital I/O or analog input.
33 P2.1 bidirectional Port 2.1 digital I/O or analog input.
34 P2.0 bidirectional Port 2.0 digital I/O or analog input; see SFR Definition 20.20 for a description.
35 P1.7 bidirectional Port 1.7 digital I/O or analog input.
36 P1.6 bidirectional Port 1.6 digital I/O or analog input.
37 P1.5 bidirectional Port 1.5 digital I/O or analog input.
38 P1.4 bidirectional Port 1.4 digital I/O or analog input.
39 P1.3 bidirectional Port 1.3 digital I/O or analog input.
40 P1.2 bidirectional Port 1.2 digital I/O or analog input.
41 P1.1 bidirectional Port 1.1 digital I/O or analog input.
42 P1.0 bidirectional Port 1.0 digital I/O or analog input; see SFR Definition 20.16 for a description.
43 P0.7 bidirectional Port 0.7 digital I/O or analog input.
44 P0.6 bidirectional Port 0.6 digital I/O or analog input.
45 P0.5 bidirectional Port 0.5 digital I/O or analog input.
46 P0.4 bidirectional Port 0.4 digital I/O or analog input.
47 P0.3 bidirectional Port 0.3 digital I/O or analog input.
48 P0.2 bidirectional Port 0.2 digital I/O or analog input.

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package QFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Temperature under Bias -55 135 °C 40
Storage Temperature -65 150 °C 40
Voltage on VREGIN with Respect to GND VREGIN -0.3 5.5 V 40
Voltage on VDD with Respect to GND VDD -0.3 2.8 V 40
Voltage on VDDA with Respect to GND VDDA -0.3 2.8 V 40
Voltage on VIO with Respect to GND VIO -0.3 5.5 V 40
Maximum Total Current through VREGIN or GND 500 mA 40
Maximum Output Current Sunk by RST or any Port Pin 100 mA 40
Maximum Output Current Sourced by any Port Pin 100 mA 40
Supply Input Voltage (VREGIN) VREGIN 1.8 5.25 V 41
Digital Supply Voltage (VDD) VDD 2.75 V System Clock < 25 MHz 41
Digital Supply Voltage (VDD) VDD 2.75 V System Clock > 25 MHz 41
Analog Supply Voltage (VDDA) VDDA 2.75 V System Clock < 25 MHz 41
Analog Supply Voltage (VDDA) VDDA 2.75 V System Clock > 25 MHz 41
Digital Supply RAM Data Retention Voltage 1.5 V 41
Port I/O Supply Voltage (VIO) VIO 1.82 5.25 V Normal Operation 41
SYSCLK (System Clock) SYSCLK 0 50 MHz 41
TSYSH (SYSCLK High Time) TSYSH 9 ns 41
TSYSL (SYSCLK Low Time) TSYSL 9 ns 41
Specified Operating Temperature Range -40 125 °C 41
Digital Supply Current, CPU Active IDD 10 11 mA CPU active, normal mode, fetching from Flash; VDD = 2.1 V, F = 25 MHz 41
Digital Supply Current, CPU Active IDD 19 21 mA CPU active, normal mode, fetching from Flash; VDD = 2.1 V, F = 50 MHz 41
Digital Supply Current, CPU Active IDD 14 21 mA CPU active, normal mode, fetching from Flash; VDD = 2.6 V, F = 25 MHz 42
Digital Supply Current, CPU Active IDD 25 33 mA CPU active, normal mode, fetching from Flash; VDD = 2.6 V, F = 50 MHz 42
Output Low Voltage VOL 50 mV VIO = 1.8 V; IOL = 70 µA 45
Output Low Voltage VOL 750 mV VIO = 1.8 V; IOL = 8.5 mA 45
Output Low Voltage VOL 45 mV VIO = 2.7 V; IOL = 70 µA 45
Output Low Voltage VOL 550 mV VIO = 2.7 V; IOL = 8.5 mA 45
Output Low Voltage VOL 40 mV VIO = 5.25 V; IOL = 70 µA 45
Output Low Voltage VOL 400 mV VIO = 5.25 V; IOL = 8.5 mA 45
RST Output Low Voltage 40 mV VIO = 5 V; IOL = 70 µA 46
RST Input Pullup Current 47 115 µA RST = 0.0 V, VIO = 5 V 46
VDD RST Threshold (VRST-LOW) VRST-LOW 1.65 1.75 1.8 V 46
VDD RST Threshold (VRST-HIGH) VRST-HIGH 2.25 2.3 2.45 V 46
Missing Clock Detector Timeout 200 370 600 µs Time from last system clock rising edge to reset initiation; VDD = 2.1 V 46
Missing Clock Detector Timeout 200 270 600 µs Time from last system clock rising edge to reset initiation; VDD = 2.5 V 46
Minimum RST Low Time to Generate a System Reset 6 µs 46
VDD Monitor Turn-on Time 60 100 µs 46
Flash Endurance 20 150 k Erase/Write 46
Flash Retention 10 years 85 °C 46
Erase Cycle Time 28 30 45 ms 25 MHz System Clock 46
Write Cycle Time 79 84 125 µs 25 MHz System Clock 46
Oscillator Frequency (VDD > VREGMIN) -0.5 0.5 % IFCN = 111b; VDD > VREGMIN; nominal 24 MHz 47
Oscillator Frequency (VDD < VREGMIN) -1 1 % IFCN = 111b; VDD < VREGMIN; nominal 24 MHz 47
Oscillator Supply Current (from VDD) 830 1300 µA Internal Oscillator On; OSCICN[7:6] = 11b 47
Clock Multiplier Input Frequency (Fcmin) Fcmin 2 MHz 48
Clock Multiplier Output Frequency 50 MHz 48
Clock Multiplier Power Supply Current 1.1 1.9 mA 48
Voltage Regulator Output Voltage (VDD) VDD 2 2.1 2.25 V 2.1 V operation (REG0MD = 0) 48
Voltage Regulator Output Voltage (VDD) VDD 2.5 2.6 2.75 V 2.6 V operation (REG0MD = 1) 48
Voltage Regulator Bias Current 1 9 µA 48
Dropout Indicator Detection Threshold -0.21 -0.02 V With respect to VDD 48
Internal Voltage Reference Output Voltage 1.45 1.5 1.55 V 25 °C ambient (REFLV = 0) 50
Internal Voltage Reference Output Voltage 2.15 2.2 2.25 V 25 °C ambient (REFLV = 1), VDD = 2.6 V 50
ADC0 Integral Nonlinearity INL -3 0.5 3 LSB 49
ADC0 Offset Error -10 -1.8 10 LSB 49
ADC0 Signal-to-Noise Plus Distortion SNDR 63 66 dB 10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps 49
ADC0 SAR Conversion Clock 3.6 MHz 49
Comparator Input Offset Voltage -10 10 mV 51
Comparator Supply Current at DC 6.2 20 µA Mode 0 51

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body 30

CAD (KiCad official)

  • Symbol: C8051F500-IQR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: QFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: c8051f500-iqr-etched.step / c8051f500-iqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f500-iqr.step / c8051f500-iqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (313 pp, sha256 a7b70c6aeb1faf1d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF