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C8051F410-GQR

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SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F410-GQR

SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

C8051F410-GQR from SKYWORKS SILICON LABS, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIO power_in I/O supply voltage for the port pins.
2 RST/C2CK bidirectional Open-drain device reset that is driven low by the internal POR or VDD monitor and can be driven low externally for at least 15 µs to reset the device (1 kΩ pullup to VIO recommended); also the clock for the C2 debug interface.
3 VRTC-BACKUP power_in smaRTClock backup supply voltage.
4 XTAL4 output smaRTClock oscillator crystal connection (Table 4.1 prints this pin as 'Crystal Input' but classifies it as an analog output).
5 XTAL3 input smaRTClock oscillator crystal input.
6 GND power_in Ground.
7 VDD power_in Core supply voltage.
8 VREGIN power_in Input to the on-chip voltage regulator.
9 P1.0/XTAL1 bidirectional Port 1.0 digital I/O or analog input; also the external clock input and oscillator return for a crystal or resonator.
10 P1.1/XTAL2 bidirectional Port 1.1 digital I/O or analog input; also the external clock output driving a crystal or resonator, or the clock input in CMOS, capacitor, or RC oscillator configurations.
11 P1.2/VREF bidirectional Port 1.2 digital I/O or analog input; also the external VREF input.
12 P1.3 bidirectional Port 1.3 digital I/O or analog input.
13 P1.4 bidirectional Port 1.4 digital I/O or analog input.
14 P1.5 bidirectional Port 1.5 digital I/O or analog input.
15 P1.6 bidirectional Port 1.6 digital I/O or analog input.
16 P1.7 bidirectional Port 1.7 digital I/O or analog input.
17 P0.0/IDAC0 bidirectional Port 0.0 digital I/O or analog input; also the IDAC0 current-mode DAC output.
18 P0.1/IDAC1 bidirectional Port 0.1 digital I/O or analog input; also the IDAC1 current-mode DAC output.
19 P0.2 bidirectional Port 0.2 digital I/O or analog input.
20 P0.3 bidirectional Port 0.3 digital I/O or analog input.
21 P0.4/TX bidirectional Port 0.4 digital I/O or analog input; also the UART TX pin, which is fixed to P0.4 for bootloading.
22 P0.5/RX bidirectional Port 0.5 digital I/O or analog input; also the UART RX pin, which is fixed to P0.5 for bootloading.
23 P0.6/CNVSTR bidirectional Port 0.6 digital I/O or analog input; also the external convert-start input for ADC0, IDA0, and IDA1.
24 P0.7 bidirectional Port 0.7 digital I/O or analog input.
25 P2.0 bidirectional Port 2.0 digital I/O or analog input.
26 P2.1 bidirectional Port 2.1 digital I/O or analog input.
27 P2.2 bidirectional Port 2.2 digital I/O or analog input.
28 P2.3 bidirectional Port 2.3 digital I/O or analog input (available only on the C8051F410/2).
29 P2.4 bidirectional Port 2.4 digital I/O or analog input (available only on the C8051F410/2).
30 P2.5 bidirectional Port 2.5 digital I/O or analog input (available only on the C8051F410/2).
31 P2.6 bidirectional Port 2.6 digital I/O or analog input (available only on the C8051F410/2).
32 P2.7/C2D bidirectional Port 2.7 digital I/O or analog input; also the bidirectional data signal for the C2 debug interface.

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 35
Storage Temperature -65 150 °C 35
Voltage on VREGIN with respect to GND VREGIN -0.3 5.5 V 35
Voltage on VDD with respect to GND VDD -0.3 3 V 35
Voltage on VRTC-BACKUP with respect to GND VRTC-BACKUP -0.3 5.5 V 35
Voltage on XTAL1 with respect to GND XTAL1 -0.3 V 35
Voltage on XTAL3 with respect to GND XTAL3 -0.3 5.5 V 35
Voltage on any Port I/O Pin (except Port 0) or RST with respect to GND VIO -0.3 V 35
Voltage on any Port 0 Pin with respect to GND 0.3 5.5 V 35
Maximum output current sunk by any Port pin 100 mA 35
Maximum output current sourced by any Port pin 100 mA 35
Maximum total current through VDD, VIO, VRTC-BACKUP, VREGIN, and GND 500 mA 35
Supply Input Voltage (VREGIN) VREGIN 2.15 5.25 V Output Current = 1 mA 36
Core Supply Voltage (VDD) VDD 2 2.75 V 36
I/O Supply Voltage (VIO) VIO 2 5.25 V 36
Backup Supply Voltage (VRTC-BACKUP) VRTC-BACKUP 1 5.25 V 36
SYSCLK (System Clock) SYSCLK 0 50 MHz 36
Specified Operating Temperature Range -40 85 °C 36
Core Supply Current (IDD), CPU active IDD 13 17 µA VDD = 2.0 V; F = 32 kHz 37
Core Supply Current (IDD), CPU active IDD 0.3 0.43 mA VDD = 2.0 V; F = 1 MHz 37
Core Supply Current (IDD), CPU active IDD 5.5 8.3 mA VDD = 2.0 V; F = 25 MHz 37
Core Supply Current (IDD), CPU active IDD 9.5 13.5 mA VDD = 2.0 V; F = 50 MHz 37
Core Supply Current (IDD), CPU active IDD 30 40 µA VDD = 2.5 V; F = 32 kHz 37
Core Supply Current (IDD), CPU active IDD 0.5 0.65 mA VDD = 2.5 V; F = 1 MHz 37
Core Supply Current (IDD), CPU active IDD 6.5 9.5 mA VDD = 2.5 V; F = 25 MHz 37
Core Supply Current (IDD), CPU active IDD 12 15 mA VDD = 2.5 V; F = 50 MHz 37
Core Supply Current (IDD), CPU inactive (Idle) IDD 10 11 µA VDD = 2.0 V; F = 32 kHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 0.15 0.21 mA VDD = 2.0 V; F = 1 MHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 2.8 3.8 mA VDD = 2.0 V; F = 25 MHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 5 7.5 mA VDD = 2.0 V; F = 50 MHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 25 30 µA VDD = 2.5 V; F = 32 kHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 0.25 0.37 mA VDD = 2.5 V; F = 1 MHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 3.3 4.3 mA VDD = 2.5 V; F = 25 MHz 38
Core Supply Current (IDD), CPU inactive (Idle) IDD 11 8 mA VDD = 2.5 V; F = 50 MHz 38
Digital Supply Current (Suspend Mode) 0.15 50 µA Oscillator not running, VDD = 2.5 V 38
Digital Supply Current (Stop Mode, shutdown) 0.15 50 µA Oscillator not running, VDD = 2.5 V 38
ADC0 Integral Nonlinearity INL -1 1 LSB VDD = 2.5 V, VREF = 2.2 V 67
ADC0 Differential Nonlinearity DNL -1 1 LSB VDD = 2.5 V, VREF = 2.2 V; Guaranteed Monotonic 67
ADC0 Offset Error -10 3 10 LSB VDD = 2.5 V, VREF = 2.2 V 67
ADC0 Full Scale Error -10 3 10 LSB VDD = 2.5 V, VREF = 2.2 V 67
ADC0 Signal-to-Noise Plus Distortion SNDR 66 69 dB Regular Mode (BURSTEN = '0'); 10 kHz sine-wave, 200 ksps 67
ADC0 Signal-to-Noise Plus Distortion SNDR 60 63 dB Burst Mode (BURSTEN = '0'); 10 kHz sine-wave, 200 ksps 67
SAR Conversion Clock 3 MHz Regular Mode (BURSTEN = '0') 67
Track/Hold Acquisition Time 1 µs 67
Throughput Rate 200 ksps 67
Power Supply Current (VDD supplied to ADC0) 680 1000 µA Operating Mode, 200 ksps 67
Internal Reference Output Voltage (REFLV = 0) 1.47 1.5 1.53 V 25 °C ambient (REFLV = 0); VDD = 2.0 V 79
Internal Reference Output Voltage (REFLV = 1) 2.16 2.2 2.24 V 25 °C ambient (REFLV = 1), VDD = 2.5 V 79
Comparator Input Offset Voltage -10 10 mV VDD = 2.0 V, -40 to +85 °C 92
Common-Mode Rejection Ratio 1.5 14 mV/V 92
Inverting or Non-Inverting Input Voltage Range -0.25 V VDD = 2.0 V 92
Power Supply Rejection (Comparator) 0.2 4 mV/V 92
Comparator Supply Current at DC, Mode 0 13 30 µA Mode 0 92
VDD Monitor Threshold (VRST-LOW) VRST-LOW 1.9 1.95 2 V 134
VDD Monitor Threshold (VRST-HIGH) VRST-HIGH 2.25 2.3 2.35 V 134
Missing Clock Detector Timeout 50 350 650 µs Time from last system clock rising edge to reset initiation 134
Reset Time Delay 180 µs Delay between release of any reset source and code execution at location 0x0000 134
VDD Ramp Time 1 ms VDD = 0 V to VDD = VRST 134
Internal Oscillator Frequency 24 24.5 25 MHz Reset Frequency 175

CAD (KiCad official)

  • Symbol: C8051F410-GQR
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: c8051f410-gqr-etched.step / c8051f410-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f410-gqr.step / c8051f410-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (270 pp, sha256 1554a9bce1c21db6, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF