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C8051F390-A-GMR

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerc8051f390-a-gmrfactory-2.0.0extractor-text

Verified C8051F390-A-GMR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F390-A-GMR · QFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 303-page datasheet
  • ✓distributor: lcsc C2054079, digikey 336-4818-2-ND, mouser 634-C8051F390-A-GMR
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7lzc1fdl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ c8051f390-a-gmr.kicad_sym✓ c8051f390-a-gmr.kicad_mod✓ c8051f390-a-gmr.step
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Symbol & Footprint

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Contents

README

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C8051F390-A-GMR

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24-EP(4x4)

C8051F390-A-GMR from SILICON LABS, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1/IDA0 bidirectional Port 0.1, digital I/O or analog input, also the IDA0 current DAC output.
2 P0.0/VREF bidirectional Port 0.0, digital I/O or analog input, also the external VREF input.
3 GND power_in Ground connection, required; the center pad may optionally be connected to ground also.
4 VDD power_in Power supply voltage.
5 RST/C2CK bidirectional Device reset open-drain output of internal POR or VDD monitor (an external source can reset the device by driving it low for at least 10 μs), and clock signal for the C2 debug interface.
6 P2.4/C2D bidirectional Port 2.4 digital I/O, shared with the bi-directional C2 debug interface data signal C2D on 24-pin packaging.
7 P2.3 bidirectional Port 2.3, digital I/O or analog input.
8 P2.2 bidirectional Port 2.2, digital I/O or analog input.
9 P2.1 bidirectional Port 2.1, digital I/O or analog input.
10 P2.0 bidirectional Port 2.0, digital I/O or analog input.
11 P1.7 bidirectional Port 1.7, digital I/O or analog input.
12 P1.6 bidirectional Port 1.6, digital I/O or analog input.
13 P1.5 bidirectional Port 1.5, digital I/O or analog input.
14 P1.4 bidirectional Port 1.4, digital I/O or analog input.
15 P1.3 bidirectional Port 1.3, digital I/O or analog input.
16 P1.2/IDA1 bidirectional Port 1.2, digital I/O or analog input, also the IDA1 current DAC output.
17 P1.1 bidirectional Port 1.1, digital I/O or analog input.
18 P1.0 bidirectional Port 1.0, digital I/O or analog input.
19 P0.7 bidirectional Port 0.7, digital I/O or analog input.
20 P0.6/CNVSTR bidirectional Port 0.6, digital I/O or analog input, also the ADC0 external convert start or IDA0 update source input.
21 P0.5 bidirectional Port 0.5, digital I/O or analog input; the Crossbar always assigns UART RX0 to this pin.
22 P0.4 bidirectional Port 0.4, digital I/O or analog input; the Crossbar always assigns UART TX0 to this pin.
23 P0.3/XTAL2 bidirectional Port 0.3, digital I/O or analog input, also the external clock output (crystal/resonator excitation driver) or external clock input for CMOS, capacitor or RC oscillator configurations.
24 P0.2/XTAL1 bidirectional Port 0.2, digital I/O or analog input, also the external oscillator return for a crystal or resonator.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-24-EP(4x4)
Category Single Chip Microcomputer/Microcontroller
Pins 25

CAD (KiCad official)

  • Symbol: C8051F390-A-GMR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: c8051f390-a-gmr-etched.step / c8051f390-a-gmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f390-a-gmr.step / c8051f390-a-gmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (303 pp, sha256 4d666090a43badcf, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF