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C8051F386-GQ

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersc8051f386-gqfactory-2.0.0extractor-text

Verified C8051F386-GQ

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F386-GQ · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 321-page datasheet
  • ✓distributor: lcsc C1522093, digikey 336-2030-ND, mouser 634-C8051F386-GQ
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-en9h1agx/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.26)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ c8051f386-gq.kicad_sym✓ c8051f386-gq.kicad_mod✓ c8051f386-gq.step
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C8051F386-GQ

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

C8051F386-GQ from SILICON LABS, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.5 bidirectional Port 0.5 is a 5 V tolerant I/O or analog input; it is fixed to UART RX0 for bootloading and cannot be reassigned by the Crossbar.
2 P0.4 bidirectional Port 0.4 is a 5 V tolerant I/O or analog input; it is fixed to UART TX0 for bootloading and cannot be reassigned by the Crossbar.
3 P0.3 bidirectional Port 0.3 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
4 P0.2 bidirectional Port 0.2 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
5 P0.1 bidirectional Port 0.1 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
6 P0.0 bidirectional Port 0.0 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
7 GND power_in Ground.
8 D+ bidirectional USB D+ signal; the transceiver is integrated and requires no external resistors.
9 D- bidirectional USB D- signal; the transceiver is integrated and requires no external resistors.
10 VDD power_in Power supply voltage input of 2.7-3.6 V; the same pin is also listed as the 3.3 V voltage regulator output.
11 REGIN power_in 5 V regulator input to the on-chip voltage regulator.
12 VBUS power_in VBUS sense input connected to the USB VBUS signal; a 5 V signal on this pin indicates a USB connection.
13 RST/C2CK bidirectional Open-drain device reset from the internal POR or VDD monitor; an external source can reset the device by driving it low for at least 15 µs. Also the C2 debug interface clock.
14 C2D bidirectional Bidirectional data signal for the C2 debug interface.
15 P4.7 bidirectional Port 4.7 is a 5 V tolerant I/O or analog input (48-pin package only).
16 P4.6 bidirectional Port 4.6 is a 5 V tolerant I/O or analog input (48-pin package only).
17 P4.5 bidirectional Port 4.5 is a 5 V tolerant I/O or analog input (48-pin package only).
18 P4.4 bidirectional Port 4.4 is a 5 V tolerant I/O or analog input (48-pin package only).
19 P4.3 bidirectional Port 4.3 is a 5 V tolerant I/O or analog input (48-pin package only).
20 P4.2 bidirectional Port 4.2 is a 5 V tolerant I/O or analog input (48-pin package only).
21 P4.1 bidirectional Port 4.1 is a 5 V tolerant I/O or analog input (48-pin package only).
22 P4.0 bidirectional Port 4.0 is a 5 V tolerant I/O or analog input (48-pin package only).
23 P3.7 bidirectional Port 3.7 is a 5 V tolerant I/O or analog input (48-pin package only).
24 P3.6 bidirectional Port 3.6 is a 5 V tolerant I/O or analog input (48-pin package only).
25 P3.5 bidirectional Port 3.5 is a 5 V tolerant I/O or analog input (48-pin package only).
26 P3.4 bidirectional Port 3.4 is a 5 V tolerant I/O or analog input (48-pin package only).
27 P3.3 bidirectional Port 3.3 is a 5 V tolerant I/O or analog input (48-pin package only).
28 P3.2 bidirectional Port 3.2 is a 5 V tolerant I/O or analog input (48-pin package only).
29 P3.1 bidirectional Port 3.1 is a 5 V tolerant I/O or analog input (48-pin package only).
30 P3.0 bidirectional Port 3.0 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
31 P2.7 bidirectional Port 2.7 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
32 P2.6 bidirectional Port 2.6 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
33 P2.5 bidirectional Port 2.5 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
34 P2.4 bidirectional Port 2.4 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
35 P2.3 bidirectional Port 2.3 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
36 P2.2 bidirectional Port 2.2 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
37 P2.1 bidirectional Port 2.1 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
38 P2.0 bidirectional Port 2.0 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
39 P1.7 bidirectional Port 1.7 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
40 P1.6 bidirectional Port 1.6 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
41 P1.5 bidirectional Port 1.5 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
42 P1.4 bidirectional Port 1.4 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
43 P1.3 bidirectional Port 1.3 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
44 P1.2 bidirectional Port 1.2 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
45 P1.1 bidirectional Port 1.1 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
46 P1.0 bidirectional Port 1.0 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
47 P0.7 bidirectional Port 0.7 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.
48 P0.6 bidirectional Port 0.6 is a 5 V tolerant I/O or analog input that can be assigned to digital resources through the Priority Crossbar.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction Temperature Under Bias -55 125 °C 37
Storage Temperature -65 150 °C 37
Voltage on RST, VBUS, or any Port I/O Pin with respect to GND -0.3 5.8 V VDD > 2.2 V 37
Voltage on RST, VBUS, or any Port I/O Pin with respect to GND -0.3 V VDD < 2.2 V; printed max is VDD + 3.6 V 37
Voltage on VDD with respect to GND, Regulator1 in Normal Mode -0.3 4.2 V Regulator1 in Normal Mode 37
Voltage on VDD with respect to GND, Regulator1 in Bypass Mode -0.3 1.98 V Regulator1 in Bypass Mode 37
Maximum Total Current through VDD or GND 500 mA 37
Maximum Output Current sunk by RST or any Port Pin 100 mA 37
Digital Supply Voltage VRST 3.3 3.6 V USB requires 3.0 V minimum supply voltage (footnote 1); printed min cell garbled 38
SYSCLK (System Clock) 0 48 MHz 38
Specified Operating Temperature Range -40 85 °C 38
Digital Supply Current, CPU Active (Normal Mode) IDD 12 14 mA SYSCLK = 48 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Active (Normal Mode) IDD 7 8 mA SYSCLK = 24 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Active (Normal Mode) IDD 0.45 0.85 mA SYSCLK = 1 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Inactive (Idle Mode) IDD 6.5 8 mA SYSCLK = 48 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Inactive (Idle Mode) IDD 3.5 5 mA SYSCLK = 24 MHz, VDD = 3.3 V 38
Input High Voltage 2 V Port I/O, VDD = 2.7 to 3.6 V 39
Input Low Voltage 0.8 V Port I/O, VDD = 2.7 to 3.6 V 39
Output Low Voltage 0.6 V IOL = 8.5 mA, Port I/O (row mapping inferred from garbled layout) 39
Output Low Voltage 0.1 V IOL = 10 µA, Port I/O (row mapping inferred from garbled layout) 39
Output Low Voltage 1 V IOL = 25 mA, Port I/O (row mapping inferred from garbled layout) 39
Input Leakage Current -1 1 µA Weak Pullup Off 39
Input Leakage Current 15 50 µA Weak Pullup On, VIN = 0 V 39
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 39
RST Input Pullup Current 15 40 µA RST = 0.0 V 39
VDD Monitor Threshold VRST 2.6 2.65 2.7 V 39
Missing Clock Detector Timeout 80 580 800 µs Time from last system clock rising edge to reset initiation 39
Reset Time Delay 250 µs Delay between release of any reset source and code execution at 0x0000 39
Minimum RST Low Time to Generate a System Reset 15 µs 39
VDD Monitor Turn-on Time 100 µs 39
VDD Monitor Supply Current 15 50 µA 39
Voltage Regulator (REG0) Input Voltage Range 2.7 5.25 V Input range specified for regulation 40
Voltage Regulator (REG0) Output Voltage (VDD) 3 3.3 3.6 V Output Current = 1 to 100 mA 40
Voltage Regulator (REG0) Output Current 100 mA 40
Voltage Regulator (REG1) Input Voltage Range 1.8 3.6 V 40
Flash Size 32768 Bytes C8051F382/3/6/7 (32 kB variant); printed as a single cell 40
Erase Cycle Time 10 15 22.5 ms 25 MHz System Clock 40
Write Cycle Time 10 15 20 µs 25 MHz System Clock 40
Internal High-Frequency Oscillator Frequency 47.3 48 48.7 MHz IFCN = 11b, factory-calibrated 41
Internal Low-Frequency Oscillator Frequency 75 80 85 kHz OSCLD = 11b, factory-calibrated 41
External Crystal Frequency 0.02 30 MHz 41
External CMOS Oscillator Frequency 0 48 MHz 41
Common-Mode Rejection Ratio 1.5 4 mV/V 44
Positive Hysteresis 1 0 1 mV CP0HYP1-0 = 00 44
Positive Hysteresis 2 2 5 10 mV CP0HYP1-0 = 01 44
Positive Hysteresis 3 7 10 20 mV CP0HYP1-0 = 10 44
Negative Hysteresis 2 2 5 10 mV CP0HYN1-0 = 01 44
Negative Hysteresis 3 7 10 20 mV CP0HYN1-0 = 10 44
Inverting or Non-Inverting Input Voltage Range -0.25 V Printed max is VDD + 0.25 V 44
Input Offset Voltage -10 10 mV 44
Transmitter Output High Voltage (VOH) VOH 2.8 V VDD = 3.0 V to 3.6 V 45
Transmitter Output Low Voltage (VOL) VOL 0.8 V VDD = 3.0 V to 3.6 V 45
VBUS Detection Input Low Voltage 1 V VDD = 3.0 V to 3.6 V 45
VBUS Detection Input High Voltage 3 V VDD = 3.0 V to 3.6 V 45
Output Crossover Point (VCRS) VCRS 1.3 2 V VDD = 3.0 V to 3.6 V 45
Pull-up Resistance (RPU), Full Speed (D+ Pull-up) RPU 1.425 1.5 1.575 kΩ Full Speed (D+ Pull-up) 45
Pull-up Resistance (RPU), Low Speed (D- Pull-up) RPU 1.425 1.5 1.575 kΩ Low Speed (D- Pull-up) 45
Differential Input Sensitivity (VDI) VDI 0.2 V /(D+), (D-)/ 45
Differential Input Common Mode Range (VCM) VCM 0.8 2.5 V 45

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body 26

CAD (KiCad official)

  • Symbol: C8051F386-GQ
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: c8051f386-gq-etched.step / c8051f386-gq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f386-gq.step / c8051f386-gq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (321 pp, sha256 1e2365a43af9ad55, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF