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C8051F381-GM

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersc8051f381-gmfactory-2.0.0extractor-text

Verified C8051F381-GM

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F381-GM · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 321-page datasheet
  • ✓distributor: lcsc C1522096, digikey 336-2022-ND, mouser 634-C8051F381-GM
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-o8pxc4yp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.32)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ c8051f381-gm.kicad_sym✓ c8051f381-gm.kicad_mod✓ c8051f381-gm.step
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C8051F381-GM

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-32-EP(5x5)

C8051F381-GM from SILICON LABS, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Port 0.1 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
2 P0.0 bidirectional Port 0.0 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
3 GND power_in Ground.
4 D+ bidirectional USB D+ signal pin.
5 D- bidirectional USB D- signal pin.
6 VDD power_in Power supply voltage input of 2.7-3.6 V; the same pin also carries the 3.3 V voltage regulator output.
7 REGIN power_in 5 V regulator input to the on-chip voltage regulator.
8 VBUS power_in VBUS sense input connected to the USB VBUS signal; a 5 V signal on this pin indicates a USB connection.
9 RST/C2CK bidirectional Device reset: open-drain output of the internal POR or VDD monitor, and an external source driving it low for at least 15 µs initiates a system reset; also the C2 debug interface clock.
10 P3.0/C2D bidirectional Port 3.0 digital I/O or analog input; also the bi-directional data signal for the C2 debug interface.
11 P2.7 bidirectional Port 2.7 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
12 P2.6 bidirectional Port 2.6 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
13 P2.5 bidirectional Port 2.5 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
14 P2.4 bidirectional Port 2.4 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
15 P2.3 bidirectional Port 2.3 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
16 P2.2 bidirectional Port 2.2 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
17 P2.1 bidirectional Port 2.1 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
18 P2.0 bidirectional Port 2.0 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
19 P1.7 bidirectional Port 1.7 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
20 P1.6 bidirectional Port 1.6 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
21 P1.5 bidirectional Port 1.5 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
22 P1.4 bidirectional Port 1.4 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
23 P1.3 bidirectional Port 1.3 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
24 P1.2 bidirectional Port 1.2 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
25 P1.1 bidirectional Port 1.1 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
26 P1.0 bidirectional Port 1.0 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
27 P0.7 bidirectional Port 0.7 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
28 P0.6 bidirectional Port 0.6 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
29 P0.5 bidirectional Port 0.5 digital I/O (push-pull or open-drain) or analog input; UART RX0 is fixed to this pin for bootloading.
30 P0.4 bidirectional Port 0.4 digital I/O (push-pull or open-drain) or analog input; UART TX0 is fixed to this pin for bootloading.
31 P0.3 bidirectional Port 0.3 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
32 P0.2 bidirectional Port 0.2 digital I/O (push-pull or open-drain) or analog input, assignable to peripherals through the crossbar.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SYSCLK (System Clock) SYSCLK 0 48 MHz 38
Specified Operating Temperature Range -40 85 °C 38
Digital Supply Current, CPU Active, SYSCLK = 48 MHz IDD 12 14 mA SYSCLK = 48 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Active, SYSCLK = 24 MHz IDD 7 8 mA SYSCLK = 24 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Active, SYSCLK = 1 MHz IDD 0.45 0.85 mA SYSCLK = 1 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Inactive (Idle), SYSCLK = 48 MHz Idle IDD 6.5 8 mA SYSCLK = 48 MHz, VDD = 3.3 V 38
Digital Supply Current, CPU Inactive (Idle), SYSCLK = 24 MHz Idle IDD 3.5 5 mA SYSCLK = 24 MHz, VDD = 3.3 V 38
Input High Voltage 2 V 39
Input Low Voltage 0.8 V 39
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 39
RST Input Pullup Current 15 40 µA RST = 0.0 V 39
VDD Monitor Threshold VRST 2.6 2.65 2.7 V 39
Missing Clock Detector Timeout 80 580 800 µs Time from last system clock rising edge to reset initiation 39
Reset Time Delay 250 µs Delay between release of any reset source and code execution at location 0x0000 39
Minimum RST Low Time to Generate a System Reset 15 µs 39
VDD Monitor Turn-on Time 100 µs 39
Digital Supply Voltage REG0 Input Voltage Range 2.7 5.25 V 40
REG0 Output Voltage (VDD) VDD 3 3.3 3.6 V Output Current = 1 to 100 mA 40
REG0 Output Current 100 mA 40
REG1 Input Voltage Range 1.8 3.6 V 40
Flash Size 65536 Bytes C8051F380/1/4/5 row (Table 5.6 footnote 1 applies) 40
Erase Cycle Time 10 15 22.5 ms 25 MHz System Clock 40
Write Cycle Time 10 15 20 µs 25 MHz System Clock 40
Internal High-Frequency Oscillator Frequency 47.3 48 48.7 MHz IFCN = 11b 41
Internal Low-Frequency Oscillator Frequency 75 80 85 kHz OSCLD = 11b 41
External Crystal Frequency 0.02 30 MHz 41
ADC0 Integral Nonlinearity -1 1 LSB 42
ADC0 Offset Error -2 0 2 LSB 42
ADC0 Full Scale Error -5 -2 0 LSB 42
ADC0 Signal-to-Noise Plus Distortion 55 58 dB 10 kHz sine-wave single-ended input, 1 dB below Full Scale, 500 ksps 42
ADC0 Conversion Time in SAR Clocks 13 clocks 10-bit Mode 42
ADC0 Power Supply Current (VDD supplied to ADC0) 750 1000 µA Operating Mode, 500 ksps 42
Internal Reference Output Voltage 2.38 2.42 2.46 V 25 °C ambient 43
VREF Short-Circuit Current 8 mA 43
Comparator Common-Mode Rejection Ratio 1.5 4 mV/V 44
Comparator Positive Hysteresis 1 0 1 mV CP0HYP1-0 = 00 44
Comparator Positive Hysteresis 2 2 5 10 mV CP0HYP1-0 = 01 44
Comparator Positive Hysteresis 3 7 10 20 mV CP0HYP1-0 = 10 44
Comparator Positive Hysteresis 4 15 20 30 mV CP0HYP1-0 = 11 44
Comparator Negative Hysteresis 1 0 1 mV CP0HYN1-0 = 00 44
Comparator Negative Hysteresis 2 2 5 10 mV CP0HYN1-0 = 01 44
Comparator Negative Hysteresis 3 7 10 20 mV CP0HYN1-0 = 10 44
Comparator Negative Hysteresis 4 15 20 30 mV CP0HYN1-0 = 11 44
Comparator Inverting or Non-Inverting Input Voltage Range -0.25 V 44
Comparator Input Offset Voltage -10 10 mV 44
USB Transmitter Output High Voltage VOH 2.8 V 45
USB Transmitter Output Low Voltage VOL 0.8 V 45
VBUS Detection Input Low Voltage 1 V 45
VBUS Detection Input High Voltage 3 V 45
Output Crossover Point VCRS 1.3 2 V 45
Pull-up Resistance (Full Speed D+ Pull-up) RPU 1.425 1.5 1.575 k Full Speed (D+ Pull-up) 45
Differential Input Sensitivity VDI 0.2 V / (D+), (D-) / 45
Junction Temperature Under Bias -55 125 °C 37
Storage Temperature -65 150 °C 37
Voltage on RST, VBUS, or any Port I/O Pin with Respect to GND -0.3 5.8 V VDD > 2.2 V 37
Voltage on RST, VBUS, or any Port I/O Pin with Respect to GND -0.3 V VDD < 2.2 V 37
Voltage on VDD with Respect to GND -0.3 4.2 V Regulator1 in Normal Mode 37
Voltage on VDD with Respect to GND -0.3 1.98 V Regulator1 in Bypass Mode 37
Maximum Total Current through VDD or GND 500 mA 37
Maximum Output Current sunk by RST or any Port Pin 100 mA 37

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body 26

CAD (KiCad official)

  • Symbol: C8051F381-GM
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: c8051f381-gm-etched.step / c8051f381-gm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f381-gm.step / c8051f381-gm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (321 pp, sha256 1e2365a43af9ad55, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF