component
C8051F321-GMR
Public Made by Adomby adom
SILICON LABS SILICON LABS, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownC8051F321-GMR
SILICON LABS · SILICON LABS · QFN-28-EP(5x5)
C8051F321-GMR from SILICON LABS, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1 | bidirectional | Port 0.1 digital I/O pin, configurable through the crossbar as a port pin or peripheral signal. |
| 2 | P0.0 | bidirectional | Port 0.0 digital I/O pin, configurable through the crossbar as a port pin or peripheral signal. |
| 3 | GND | power_in | Ground reference for the device. |
| 4 | D+ | bidirectional | USB D+ data line for the integrated full-speed/low-speed USB transceiver. |
| 5 | D- | bidirectional | USB D- data line for the integrated full-speed/low-speed USB transceiver. |
| 6 | VDD | power_in | Power supply voltage input of 2.7-3.6 V; the datasheet also lists a 3.3 V voltage regulator output on this pin. |
| 7 | REGIN | power_in | 5 V regulator input to the on-chip voltage regulator. |
| 8 | VBUS | power_in | VBUS sense input connected to the USB VBUS signal; a 5 V signal on this pin indicates a USB connection. |
| 9 | /RST/C2CK | bidirectional | Device reset open-drain output of the POR or VDD monitor, which an external source can drive low for at least 15 µs; also the C2 debug interface clock. |
| 10 | P3.0/C2D | bidirectional | Port 3.0 GPIO pin that doubles as the bidirectional data signal for the C2 debug interface. |
| 11 | P2.3 | bidirectional | Port 2.3 digital I/O or analog input pin, available to the crossbar. |
| 12 | P2.2 | bidirectional | Port 2.2 digital I/O or analog input pin, available to the crossbar. |
| 13 | P2.1 | bidirectional | Port 2.1 digital I/O or analog input pin, available to the crossbar. |
| 14 | P2.0 | bidirectional | Port 2.0 digital I/O or analog input pin, available to the crossbar. |
| 15 | P1.7 | bidirectional | Port 1.7 digital I/O or analog input pin, available to the crossbar. |
| 16 | P1.6 | bidirectional | Port 1.6 digital I/O or analog input pin, available to the crossbar. |
| 17 | P1.5 | bidirectional | Port 1.5 digital I/O or analog input pin, available to the crossbar. |
| 18 | P1.4 | bidirectional | Port 1.4 digital I/O or analog input pin, available to the crossbar. |
| 19 | P1.3 | bidirectional | Port 1.3 digital I/O or analog input pin, available to the crossbar. |
| 20 | P1.2 | bidirectional | Port 1.2 digital I/O or analog input pin, available to the crossbar. |
| 21 | P1.1 | bidirectional | Port 1.1 digital I/O or analog input pin, available to the crossbar. |
| 22 | P1.0 | bidirectional | Port 1.0 digital I/O or analog input pin, available to the crossbar. |
| 23 | P0.7/VREF | bidirectional | Port 0.7 digital I/O pin that also serves as the external VREF input or output. |
| 24 | P0.6/CNVSTR | bidirectional | Port 0.6 digital I/O pin that also serves as the ADC0 external convert start input. |
| 25 | P0.5 | bidirectional | Port 0.5 digital I/O pin, configurable through the crossbar as a port pin or peripheral signal. |
| 26 | P0.4 | bidirectional | Port 0.4 digital I/O pin, configurable through the crossbar as a port pin or peripheral signal. |
| 27 | P0.3/XTAL2 | bidirectional | Port 0.3 digital I/O pin that serves as the external oscillator excitation driver for a crystal or resonator, or an external clock input. |
| 28 | P0.2/XTAL1 | bidirectional | Port 0.2 digital I/O pin that serves as the external oscillator return for a crystal or resonator, or an external clock input. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | QFN-28-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -55 | 125 | °C | 29 | |||
| Storage Temperature | -65 | 150 | °C | 29 | |||
| Voltage on any Port I/O Pin or /RST with respect to GND | -0.3 | 5.8 | V | 29 | |||
| Voltage on VDD with respect to GND | -0.3 | 4.2 | V | 29 | |||
| Maximum Total current through VDD and GND | 500 | mA | 29 | ||||
| Maximum output current sunk by /RST or any Port pin | 100 | mA | 29 | ||||
| Digital Supply Voltage | VRST | 3 | 3.6 | V | 30 | ||
| Digital Supply RAM Data Retention Voltage | 1.5 | V | 30 | ||||
| SYSCLK (System Clock) | 0 | 25 | MHz | 30 | |||
| TSYSH (SYSCLK High Time) | TSYSH | 18 | ns | 30 | |||
| TSYSL (SYSCLK Low Time) | TSYSL | 18 | ns | 30 | |||
| Specified Operating Temperature Range | -40 | 85 | °C | 30 | |||
| Digital Supply Current - CPU Active, IDD | IDD | 12.3 | 13.6 | mA | VDD = 3.6 V; F = 25 MHz | 30 | |
| Digital Supply Current - CPU Active, IDD | IDD | 10.6 | 11.5 | mA | VDD = 3.3 V, F = 24 MHz | 30 | |
| Digital Supply Current - CPU Active, IDD | IDD | 9 | 9.8 | mA | VDD = 3.0 V, F = 24 MHz | 30 | |
| Digital Supply Current - CPU Idle, Idle IDD | Idle IDD | 5.8 | 6.5 | mA | VDD = 3.6 V; F = 25 MHz | 30 | |
| Digital Supply Current - CPU Idle, Idle IDD | Idle IDD | 5.2 | 5.9 | mA | VDD = 3.3 V, F = 24 MHz | 30 | |
| Digital Supply Current - CPU Idle, Idle IDD | Idle IDD | 4.6 | 5.2 | mA | VDD = 3.0 V, F = 24 MHz | 30 | |
| Input Voltage Range | 2.7 | 5.25 | V | 70 | |||
| Output Voltage (VDD) | VDD | 3 | 3.3 | 3.6 | V | Output Current = 1 to 100 mA | 70 |
| Output Current | 100 | mA | 70 | ||||
| VBUS Detection Input Low Voltage | 1 | V | 70 | ||||
| VBUS Detection Input High Voltage | 3 | V | 70 | ||||
| Dropout Voltage (VDO) | VDO | 1 | mV/mA | 70 | |||
| Integral Nonlinearity | -1 | 1 | LSB | 56 | |||
| Differential Nonlinearity | -1 | 1 | LSB | Guaranteed Monotonic | 56 | ||
| Offset Error | -15 | 0 | 15 | LSB | 56 | ||
| Full Scale Error | -15 | -1 | 15 | LSB | 56 | ||
| Offset Temperature Coefficient | 10 | ppm/°C | 56 | ||||
| Signal-to-Noise Plus Distortion | SNDR | 53 | 55.5 | dB | 10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps | 56 | |
| Total Harmonic Distortion | THD | -67 | dB | Up to the 5th harmonic | 56 | ||
| Spurious-Free Dynamic Range | SFDR | 78 | dB | 56 | |||
| SAR Conversion Clock | 3 | MHz | 56 | ||||
| Conversion Time in SAR Clocks | 10 | clocks | 56 | ||||
| Track/Hold Acquisition Time | 300 | ns | 56 | ||||
| Throughput Rate | 200 | ksps | 56 | ||||
| Input Capacitance | 5 | pF | 56 | ||||
| Temperature Sensor Linearity | 0.1 | °C | 56 | ||||
| Temperature Sensor Gain | 2.86 | mV/°C | 56 | ||||
| Temperature Sensor Offset | -8.5 | 0.776 | 8.5 | mV | Temp = 0 °C | 56 | |
| Power Supply Current (VDD supplied to ADC0) | 400 | 900 | µA | Operating Mode, 200 ksps | 56 | ||
| Power Supply Rejection | -0.3 | 0.3 | mV/V | 56 | |||
| Output Voltage 25 °C ambient (Internal Reference) | 2.38 | 2.44 | 2.5 | V | 25 °C ambient | 58 | |
| VREF Short-Circuit Current | 10 | mA | 58 | ||||
| VREF Temperature Coefficient | 15 | ppm/°C | 58 | ||||
| Load Regulation | 1.5 | ppm/µA | Load = 0 to 200 µA to GND | 58 | |||
| VREF Turn-on Time 1 | 2 | ms | 4.7 µF tantalum, 0.1 µF ceramic bypass | 58 | |||
| VREF Turn-on Time 2 | 20 | µs | 0.1 µF ceramic bypass | 58 | |||
| VREF Turn-on Time 3 | 10 | µs | no bypass cap | 58 | |||
| Power Supply Rejection (VREF) | 140 | ppm/V | 58 | ||||
| Input Current | 12 | µA | Sample Rate = 200 ksps; VREF = 3.0 V | 58 | |||
| Response Time Mode 0 | 100 | ns | Mode 0, Vcm* = 1.5 V; CP0+, CP0- = 100 mV | 68 | |||
| Response Time Mode 0 | 250 | ns | Mode 0, Vcm* = 1.5 V; CP0+, CP0- = -100 mV | 68 | |||
| Response Time Mode 3 | 1050 | ns | Mode 3, Vcm* = 1.5 V; CP0+, CP0- = 100 mV | 68 | |||
| Response Time Mode 3 | 5200 | ns | Mode 3, Vcm* = 1.5 V; CP0+, CP0- = -100 mV | 68 | |||
| Common-Mode Rejection Ratio | CMRR | 1.5 | 4 | mV/V | 68 | ||
| Positive Hysteresis 4 | 15 | 20 | 30 | mV | CP0HYP1-0 = 11 | 68 | |
| Negative Hysteresis 4 | 15 | 20 | 30 | mV | CP0HYN1-0 = 11 | 68 | |
| Inverting or Non-Inverting Input Voltage Range | -0.25 | V | 68 | ||||
| Input Capacitance (Comparator) | 3 | pF | 68 | ||||
| Input Offset Voltage | -5 | 5 | mV | 68 | |||
| Power-up Time | 10 | µs | 68 | ||||
| Supply Current at DC Mode 0 | 7.6 | 20 | µA | Mode 0 | 68 | ||
| Supply Current at DC Mode 3 | 0.4 | 2.5 | µA | Mode 3 | 68 | ||
| /RST Output Low Voltage | 0.6 | V | IOL = 8.5 mA, VDD = 2.7 V to 3.6 V | 107 | |||
| VDD POR Threshold | VRST | 2.4 | 2.55 | 2.7 | V | 107 | |
| Missing Clock Detector Timeout | 100 | 220 | 500 | µs | Time from last system clock rising edge to reset initiation | 107 | |
| Minimum /RST Low Time to Generate a System Reset | 15 | µs | 107 | ||||
| Flash Size | 16384 | bytes | 110 | ||||
| Erase Cycle Time | 10 | 15 | 20 | ms | 25 MHz System Clock | 110 | |
| Write Cycle Time | 40 | 55 | 70 | µs | 25 MHz System Clock | 110 | |
| Internal Oscillator Frequency | 11.82 | 12 | 12.18 | MHz | Reset Frequency | 128 | |
| USB Clock Frequency | 47.88 | 48 | 48.12 | MHz | Full Speed Mode; applies only to external oscillator sources | 128 | |
| USB Clock Frequency | 5.91 | 6 | 6.09 | MHz | Low Speed Mode; applies only to external oscillator sources | 128 | |
| Output Low Voltage | 1 | V | IOL = 8.5 mA, Port I/O push-pull | 141 | |||
| Output Low Voltage | 0.6 | V | IOL = 10 µA, Port I/O push-pull | 141 | |||
| Output Low Voltage | 0.1 | V | IOL = 25 mA, Port I/O push-pull | 141 | |||
| Input High Voltage | 2 | V | 141 | ||||
| Input Low Voltage | 0.8 | V | 141 | ||||
| Output High Voltage | VOH | 2.8 | V | 172 | |||
| Output Low Voltage | VOL | 0.8 | V | 172 | |||
| Pull-up Resistance Full Speed (D+ Pull-up) | RPU | 1.425 | 1.5 | 1.575 | kΩ | Full Speed | 172 |
| Pull-up Resistance Low Speed (D- Pull-up) | RPU | 1.425 | 1.5 | 1.575 | kΩ | Low Speed | 172 |
| Output Rise Time | TR | 75 | 300 | ns | Low Speed | 172 | |
| Output Rise Time | TR | 4 | 20 | ns | Full Speed | 172 | |
| Output Fall Time | TF | 75 | 300 | ns | Low Speed | 172 | |
| Output Fall Time | TF | 4 | 20 | ns | Full Speed | 172 | |
| Differential Input Sensitivity | VDI | 0.2 | V | /(D+), (D-)/ | 172 | ||
| Differential Input Common Mode Range | VCM | 0.8 | 2.5 | V | 172 | ||
| Input Leakage Current | IL | 1 | µA | Pullups Disabled | 172 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body Components. | 36 |
CAD (KiCad official)
- Symbol:
C8051F321-GMR - Footprint:
Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm - 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
c8051f321-gmr-etched.step/c8051f321-gmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);c8051f321-gmr.step/c8051f321-gmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (254 pp, sha256
46143e2ba725954a, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).