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C8051F317-GM

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SKYWORKS/SILICON LABS Microcontrollers (MCU/MPU/SOC), QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F317-GM

SKYWORKS/SILICON LABS · Microcontrollers (MCU/MPU/SOC) · QFN-24(4x4)

C8051F317-GM from SKYWORKS/SILICON LABS, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Port 0.1 digital I/O pin (see Section 13 of the datasheet).
2 P0.0/VREF bidirectional Port 0.0 digital I/O, also the external VREF analog input.
3 GND power_in Ground.
4 VDD power_in Power supply voltage, 2.7 to 3.6 V.
5 RST/C2CK bidirectional Device reset, open-drain output of the internal POR (an external source resets the system by driving it low for at least 10 µs), and clock signal for the C2 debug interface.
6 P3.0/C2D bidirectional Port 3.0 digital I/O and bi-directional data signal for the C2 debug interface.
7 P2.5 bidirectional Port 2.5 digital I/O or analog input.
8 P2.4 bidirectional Port 2.4 digital I/O or analog input.
9 P2.3 bidirectional Port 2.3 digital I/O or analog input.
10 P2.2 bidirectional Port 2.2 digital I/O or analog input.
11 P2.1 bidirectional Port 2.1 digital I/O or analog input.
12 P2.0 bidirectional Port 2.0 digital I/O or analog input.
13 P1.5 bidirectional Port 1.5 digital I/O or analog input.
14 P1.4 bidirectional Port 1.4 digital I/O or analog input.
15 P1.3 bidirectional Port 1.3 digital I/O or analog input.
16 P1.2 bidirectional Port 1.2 digital I/O or analog input.
17 P1.1 bidirectional Port 1.1 digital I/O or analog input.
18 P1.0 bidirectional Port 1.0 digital I/O or analog input.
19 P0.7 bidirectional Port 0.7 digital I/O pin.
20 P0.6 bidirectional Port 0.6 digital I/O, also the ADC0 external convert start input.
21 P0.5 bidirectional Port 0.5 digital I/O pin; UART0 RX is fixed to this pin when the UART is enabled.
22 P0.4 bidirectional Port 0.4 digital I/O pin; UART0 TX is fixed to this pin when the UART is enabled.
23 P0.3/XTAL2 bidirectional Port 0.3 digital I/O, also external clock output (crystal/resonator excitation driver) or external clock input for CMOS, capacitor or RC oscillator configurations.
24 P0.2/XTAL1 bidirectional Port 0.2 digital I/O, also external clock input (external oscillator return for a crystal or resonator).
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SKYWORKS/SILICON LABS
Package QFN-24(4x4)
Category Embedded Processors & Controllers
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 35
Storage Temperature -65 150 °C 35
Voltage on any Port I/O Pin or RST with respect to GND -0.3 5.8 V 35
Voltage on VDD with respect to GND VDD -0.3 4.2 V 35
Maximum Total current through VDD and GND 500 mA 35
Maximum output current sunk by RST or any Port pin 100 mA 35
Digital Supply Voltage VDD 3 3.6 V VRST (Note 1) 36
Specified Operating Temperature Range -40 85 °C 36
SYSCLK (system clock frequency) SYSCLK 0 25 MHz 36
SYSCLK low time Tsysl 18 ns 36
SYSCLK high time Tsysh 18 ns 36
Digital Supply Current - CPU Active IDD 7.8 8.6 mA VDD = 3.0 V, F = 25 MHz 36
Digital Supply Current - CPU Active IDD 10.7 12.1 mA VDD = 3.6 V, F = 25 MHz 36
Digital Supply Current - CPU Inactive (Idle) IDD 3.8 4.3 mA VDD = 3.0 V, F = 25 MHz 37
Digital Supply Current - CPU Inactive (Idle) IDD 4.8 5.3 mA VDD = 3.6 V, F = 25 MHz 37
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 to 3.6 V 110
RST Input High Voltage 0.7 x VDD 110
RST Input Low Voltage 0.3 x VDD 110
RST Input Pullup Current 25 40 µA RST = 0.0 V 110
VDD Monitor Threshold VRST 2.4 2.55 2.7 V 110
Missing Clock Detector Timeout 100 220 600 µs Time from last system clock rising edge to reset initiation 110
Reset Time Delay 5 µs Delay between release of any reset source and code execution at location 0x0000 110
Minimum RST Low Time to Generate a System Reset 15 µs 110
VDD Monitor Turn-on Time 100 µs 110
VDD Monitor Supply Current 20 50 µA 110
VDD Ramp Time 1 ms VDD = 0 V to VDD = 2.7 V 110
Flash Size 16384 bytes C8051F310/1/6/7 112
Flash Erase Cycle Time 10 15 20 ms 25 MHz System Clock 112
Flash Write Cycle Time 40 55 70 µs 25 MHz System Clock 112
Internal Oscillator Frequency 24 24.5 25 MHz 123
Internal Oscillator Supply Current (from VDD) 450 1000 µA OSCICN.7 = 1 123
Comparator Common-Mode Rejection Ratio 1.5 4 mV/V 78
Comparator Positive Hysteresis 1 0 1 mV CP0HYP1-0 = 00 78
Comparator Positive Hysteresis 2 2 5 7 mV CP0HYP1-0 = 01 78
Comparator Positive Hysteresis 3 5 10 13 mV CP0HYP1-0 = 10 78
Comparator Positive Hysteresis 4 12 20 25 mV CP0HYP1-0 = 11 78
Comparator Negative Hysteresis 2 2 5 7 mV CP0HYN1-0 = 01 78
Comparator Negative Hysteresis 3 5 10 13 mV CP0HYN1-0 = 10 78
Comparator Negative Hysteresis 4 12 20 25 mV CP0HYN1-0 = 11 78
Comparator Inverting or Non-Inverting Input Voltage Range -0.25 V upper limit printed as VDD + 0.25 78
Comparator Input Offset Voltage -5 5 mV 78
Comparator Power Supply Rejection 0.1 1 mV/V 78
Comparator Supply Current at DC, Mode 0 7.6 20 µA 78
Comparator Supply Current at DC, Mode 1 3.2 10 µA 78
Comparator Supply Current at DC, Mode 2 1.3 5 µA 78
Comparator Supply Current at DC, Mode 3 0.4 2.5 µA 78
Digital Supply RAM Data Retention Voltage 1.5 V 36
Digital Supply Current (Stop Mode, shutdown) 0.1 µA Oscillator not running, VDD Monitor Disabled; printed as < 0.1 37
Comparator Input Capacitance 7 pF 78
Comparator Power-up Time 10 µs 78

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body 43

CAD (KiCad official)

  • Symbol: C8051F317-GM
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: c8051f317-gm-etched.step / c8051f317-gm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f317-gm.step / c8051f317-gm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS/SILICON LABS datasheet (228 pp, sha256 20ef9aedb3ff2818, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF