# C8051F300-GMR

**SILICON LABS** · SILICON LABS · WSON-10-EP(3x3)

C8051F300-GMR from SILICON LABS, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF/P0.0 | power_in | External voltage reference input or Port 0.0, a digital I/O or analog input. |
| 2 | P0.1 | bidirectional | Port 0.1, a digital I/O or analog input. |
| 3 | VDD | power_in | Power supply voltage, 2.7 to 3.6 V. |
| 4 | XTAL1/P0.2 | bidirectional | Analog-input crystal pin that is the external oscillator circuit return for a crystal or ceramic resonator, or Port 0.2 as a digital I/O or analog input. |
| 5 | XTAL2/P0.3 | bidirectional | Crystal excitation driver (analog output) or external clock input for CMOS, capacitor or RC configurations, or Port 0.3 as a digital I/O. |
| 6 | P0.4 | bidirectional | Port 0.4, a digital I/O or analog input; UART TX0 is always assigned to this pin when selected. |
| 7 | P0.5 | bidirectional | Port 0.5, a digital I/O or analog input; UART RX0 is always assigned to this pin when selected. |
| 8 | C2CK/RST | bidirectional | Clock signal for the C2 development interface and device reset, an open-drain output of the internal POR or VDD monitor that an external source can drive low for at least 10 µs to reset the system. |
| 9 | P0.6/CNVSTR | bidirectional | Port 0.6, a digital I/O or analog input, or the ADC external convert start input strobe. |
| 10 | C2D/P0.7 | bidirectional | Data signal for the C2 development interface or Port 0.7, a digital I/O or analog input. |
| 11 | GND | power_in | Ground, which is the center exposed pad of the QFN package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | WSON-10-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 11 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body | 29 |

## CAD (KiCad official)

- Symbol: `C8051F300-GMR`
- Footprint: `Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm`
- 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `c8051f300-gmr-etched.step` / `c8051f300-gmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `c8051f300-gmr.step` / `c8051f300-gmr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [SILICON LABS datasheet](docs/c8051f300-gmr-datasheet.pdf) (178 pp, sha256 `e85f1b2727e2de75`, retrieved 2026-11-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/c8051f300-gmr-datasheet.pdf)