component

C8051F133-GQR

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SKYWORKS/SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersc8051f133-gqrfactory-2.0.0extractor-text

Changed since verified C8051F133-GQR

by Ray · last 31 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 64 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F133-GQR · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 350-page datasheet
  • ✓distributor: lcsc C3228467, digikey C8051F133-GQR-ND, mouser 634-C8051F133-GQR
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-w72tlc7n/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! c8051f133-gqr.kicad_sym✓ c8051f133-gqr.kicad_mod✓ c8051f133-gqr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers c8051f133-gqr: symbol repaired (body fitted to the names) · Ray
c8051f133-gqr-etched.glb Publish 0.1.0 · Ray
c8051f133-gqr-etched.step c8051f133-gqr: factory component page (tier=lcsc) · Ray
c8051f133-gqr-hero.glb c8051f133-gqr: hero GLB from the etched model (keeps the MPN mark) · Ray
c8051f133-gqr-hero.overlay.json Publish 0.1.0 · Ray
c8051f133-gqr.glb Publish 0.1.0 · Ray
c8051f133-gqr.kicad_mod Publish 0.1.0 · Ray
c8051f133-gqr.kicad_sym c8051f133-gqr: symbol repaired (body fitted to the names) · Ray
c8051f133-gqr.lbr c8051f133-gqr: symbol repaired (body fitted to the names) · Ray
c8051f133-gqr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 64 pins · Ray

C8051F133-GQR

SKYWORKS/SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

C8051F133-GQR from SKYWORKS/SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
24 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
41 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
57 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
25 DGND power_in Digital ground, must be tied to ground.
40 DGND power_in Digital ground, must be tied to ground.
56 DGND power_in Digital ground, must be tied to ground.
6 AV+ power_in Analog supply voltage, must be tied to +2.7 to +3.6 V.
5 AGND power_in Analog ground, must be tied to ground.
58 TMS input JTAG Test Mode Select with internal pullup.
59 TCK input JTAG Test Clock with internal pullup.
60 TDI input JTAG Test Data Input with internal pullup, latched on the rising edge of TCK.
61 TDO tri_state JTAG Test Data Output with internal pullup, shifted out on the falling edge of TCK; tri-state driver.
62 RST bidirectional Device reset; open-drain output of the internal VDD monitor, driven low when VDD < VRST and MONEN is high, and an external source can force a reset by driving it low.
17 XTAL1 input Crystal input, return for the internal oscillator circuit for a crystal or ceramic resonator; becomes the system clock if overdriven by an external CMOS clock.
18 XTAL2 output Crystal output, the excitation driver for a crystal or ceramic resonator.
19 MONEN input VDD monitor enable; tied high enables the internal VDD monitor, tied low disables it, and the pin must be tied high or low.
7 VREF power_in Bandgap voltage reference output.
8 VREF0 input ADC0 voltage reference input.
9 AIN0.0 input ADC0 input channel 0.
10 AIN0.1 input ADC0 input channel 1.
11 AIN0.2 input ADC0 input channel 2.
12 AIN0.3 input ADC0 input channel 3.
13 AIN0.4 input ADC0 input channel 4.
14 AIN0.5 input ADC0 input channel 5.
15 AIN0.6 input ADC0 input channel 6.
16 AIN0.7 input ADC0 input channel 7.
4 CP0+ input Comparator 0 non-inverting input.
3 CP0- input Comparator 0 inverting input.
2 CP1+ input Comparator 1 non-inverting input.
1 CP1- input Comparator 1 inverting input.
55 P0.0 bidirectional Port 0.0 general-purpose I/O, assignable through the crossbar.
54 P0.1 bidirectional Port 0.1 general-purpose I/O, assignable through the crossbar.
53 P0.2 bidirectional Port 0.2 general-purpose I/O, assignable through the crossbar.
52 P0.3 bidirectional Port 0.3 general-purpose I/O, assignable through the crossbar.
51 P0.4 bidirectional Port 0.4 general-purpose I/O, assignable through the crossbar.
50 ALE/P0.5 bidirectional Port 0.5 I/O or ALE strobe for the external memory address bus (multiplexed mode).
49 RD/P0.6 bidirectional Port 0.6 I/O or /RD strobe for the external memory bus.
48 WR/P0.7 bidirectional Port 0.7 I/O or /WR strobe for the external memory bus.
29 A8/P1.0 bidirectional Port 1.0 I/O or bit 8 of the external memory address bus (non-multiplexed mode).
28 A9/P1.1 bidirectional Port 1.1 I/O or external memory address bit 9 (non-multiplexed mode).
27 A10/P1.2 bidirectional Port 1.2 I/O or external memory address bit 10 (non-multiplexed mode).
26 A11/P1.3 bidirectional Port 1.3 I/O or external memory address bit 11 (non-multiplexed mode).
23 A12/P1.4 bidirectional Port 1.4 I/O or external memory address bit 12 (non-multiplexed mode).
22 A13/P1.5 bidirectional Port 1.5 I/O or external memory address bit 13 (non-multiplexed mode).
21 A14/P1.6 bidirectional Port 1.6 I/O or external memory address bit 14 (non-multiplexed mode).
20 A15/P1.7 bidirectional Port 1.7 I/O or external memory address bit 15 (non-multiplexed mode).
37 A8m/A0/P2.0 bidirectional Port 2.0 I/O or external memory address bit 8 (multiplexed) / bit 0 (non-multiplexed).
36 A9m/A1/P2.1 bidirectional Port 2.1 I/O or external memory address bit 9 (multiplexed) / bit 1 (non-multiplexed).
35 A10m/A2/P2.2 bidirectional Port 2.2 I/O or external memory address bit 10 (multiplexed) / bit 2 (non-multiplexed).
34 A11m/A3/P2.3 bidirectional Port 2.3 I/O or external memory address bit 11 (multiplexed) / bit 3 (non-multiplexed).
33 A12m/A4/P2.4 bidirectional Port 2.4 I/O or external memory address bit 12 (multiplexed) / bit 4 (non-multiplexed).
32 A13m/A5/P2.5 bidirectional Port 2.5 I/O or external memory address bit 13 (multiplexed) / bit 5 (non-multiplexed).
31 A14m/A6/P2.6 bidirectional Port 2.6 I/O or external memory address bit 14 (multiplexed) / bit 6 (non-multiplexed).
30 A15m/A7/P2.7 bidirectional Port 2.7 I/O or external memory address bit 15 (multiplexed) / bit 7 (non-multiplexed).
47 AD0/D0/P3.0 bidirectional Port 3.0 I/O or external memory address/data bit 0 (multiplexed) / data bit 0 (non-multiplexed).
46 AD1/D1/P3.1 bidirectional Port 3.1 I/O or external memory address/data bit 1 (multiplexed) / data bit 1 (non-multiplexed).
45 AD2/D2/P3.2 bidirectional Port 3.2 I/O or external memory address/data bit 2 (multiplexed) / data bit 2 (non-multiplexed).
44 AD3/D3/P3.3 bidirectional Port 3.3 I/O or external memory address/data bit 3 (multiplexed) / data bit 3 (non-multiplexed).
43 AD4/D4/P3.4 bidirectional Port 3.4 I/O or external memory address/data bit 4 (multiplexed) / data bit 4 (non-multiplexed).
42 AD5/D5/P3.5 bidirectional Port 3.5 I/O or external memory address/data bit 5 (multiplexed) / data bit 5 (non-multiplexed).
39 AD6/D6/P3.6 bidirectional Port 3.6 I/O or external memory address/data bit 6 (multiplexed) / data bit 6 (non-multiplexed).
38 AD7/D7/P3.7 bidirectional Port 3.7 I/O or external memory address/data bit 7 (multiplexed) / data bit 7 (non-multiplexed).
63 NC unconnected No connection.
64 NC unconnected No connection.

Key specifications

Parameter Value
Manufacturer SKYWORKS/SILICON LABS
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 38
Storage Temperature -65 150 °C 38
Voltage on any Pin (except VDD and Port I/O) with respect to DGND -0.3 V Max is VDD + 0.3 V 38
Voltage on any Port I/O Pin or RST with respect to DGND -0.3 5.8 V 38
Voltage on VDD with respect to DGND VDD -0.3 4.2 V 38
Maximum Total Current through VDD, AV+, DGND, and AGND 800 mA 38
Maximum Output Current Sunk by any Port pin 100 mA 38
Maximum Output Current Sunk by any other I/O pin 50 mA 38
Maximum Output Current Sourced by any Port pin 100 mA 38
Maximum Output Current Sourced by any other I/O Pin 50 mA 38
Analog Supply Voltage AV+ 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Analog Supply Voltage AV+ 3 3.3 3.6 V SYSCLK > 50 MHz 39
Digital Supply Voltage VDD 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Digital Supply Voltage VDD 3 3.3 3.6 V SYSCLK > 50 MHz 39
Analog-to-Digital Supply Delta (/VDD, AV+/) 0.5 V 39
SYSCLK (System Clock) SYSCLK 0 50 MHz VDD, AV+ = 2.7 to 3.6 V 39
SYSCLK (System Clock) SYSCLK 0 100 MHz VDD, AV+ = 3.0 to 3.6 V 39
Specified Operating Temperature Range -40 85 °C 39
Analog Supply Current 1.7 mA Internal REF, ADCs, DACs, Comparators all active 39
Digital Supply Current with CPU active 65 mA VDD = 3.0 V, Clock = 100 MHz 39
Digital Supply Current (shutdown) 0.4 μA Oscillator not running 39
Digital Supply RAM Data Retention Voltage 1.5 V 39
ADC0 Integral Nonlinearity INL -1 1 LSB 90
ADC0 Differential Nonlinearity DNL -1 1 LSB Guaranteed Monotonic 90
ADC0 Signal-to-Noise Plus Distortion 59 dB 10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps 90
ADC0 SAR Clock Frequency 2.5 MHz 90
ADC0 Conversion Time in SAR Clocks 16 clocks 90
ADC0 Track/Hold Acquisition Time 1.5 μs 90
ADC0 Throughput Rate 100 ksps 90
ADC0 Input Voltage Range 0 V Single-ended operation; max is VREF 90
ADC0 Power Supply Current (AV+ supplied to ADC) 450 900 μA Operating Mode, 100 ksps 90
Internal Reference Output Voltage 2.36 2.43 2.48 V 25 °C ambient 118
VREF Short-Circuit Current 30 mA 118
External Reference Input Voltage Range 1 V REFBE = 0; max is (AV+), 0.3 118
External Reference Input Current 0 1 μA REFBE = 0 118
VREF Temperature Coefficient 15 ppm/°C 118
Comparator Common-Mode Rejection Ratio 1.5 4 mV/V 126
Comparator Positive Hysteresis 2 2 4.5 7 mV CPnHYP1-0 = 01 126
Comparator Positive Hysteresis 3 4 9 13 mV CPnHYP1-0 = 10 126
Comparator Positive Hysteresis 4 10 17 25 mV CPnHYP1-0 = 11 126
Comparator Input Voltage Range -0.25 V Inverting or Non-Inverting; max is (AV+) + 0.25 126
Comparator Input Bias Current -5 0.001 5 nA 126
Comparator Input Offset Voltage -10 10 mV 126
Comparator Power Supply Rejection 0.1 1 mV/V 126
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 to 3.6 V 183
VDD for RST Output Valid 1 V 183
VDD POR Threshold VRST 2.4 2.55 2.7 V 183
Minimum RST Low Time to Generate a System Reset 10 ns 183
Reset Time Delay 80 100 120 ms RST rising edge after VDD crosses VRST threshold 183
Missing Clock Detector Timeout 100 220 500 μs Time from last system clock to reset initiation 183
Calibrated Internal Oscillator Frequency 24 24.5 25 MHz 185
External Clock Frequency 0 30 MHz 185
External Clock High Time TXCH 15 ns 185
External Clock Low Time TXCL 15 ns 185
Flash Erase Cycle Time 10 12 14 ms VDD = 2.7 to 3.6 V; -40 to +85 °C 200
Flash Write Cycle Time 40 50 60 μs VDD = 2.7 to 3.6 V; -40 to +85 °C 200

CAD (KiCad official)

  • Symbol: C8051F133-GQR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: c8051f133-gqr-etched.step / c8051f133-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f133-gqr.step / c8051f133-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS/SILICON LABS datasheet (350 pp, sha256 de2e31cf5b17be5e, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF