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C8051F130-GQ

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerc8051f130-gqfactory-2.0.0extractor-text

Changed since verified C8051F130-GQ

by Ray · last 31 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 100 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F130-GQ · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 350-page datasheet
  • ✓distributor: lcsc C3235918, digikey 336-1232-ND, mouser 634-C8051F130-GQ
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-40_b_uch/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! c8051f130-gq.kicad_sym✓ c8051f130-gq.kicad_mod✓ c8051f130-gq.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers c8051f130-gq: symbol repaired (body fitted to the names) · Ray
c8051f130-gq-etched.glb Publish 0.1.0 · Ray
c8051f130-gq-etched.step c8051f130-gq: factory component page (tier=lcsc) · Ray
c8051f130-gq-hero.glb c8051f130-gq: hero GLB from the etched model (keeps the MPN mark) · Ray
c8051f130-gq-hero.overlay.json Publish 0.1.0 · Ray
c8051f130-gq.glb Publish 0.1.0 · Ray
c8051f130-gq.kicad_mod Publish 0.1.0 · Ray
c8051f130-gq.kicad_sym c8051f130-gq: symbol repaired (body fitted to the names) · Ray
c8051f130-gq.lbr c8051f130-gq: symbol repaired (body fitted to the names) · Ray
c8051f130-gq.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 100 pins · Ray

C8051F130-GQ

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(14x14)

C8051F130-GQ from SILICON LABS, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS input JTAG Test Mode Select with internal pullup.
2 TCK input JTAG Test Clock with internal pullup.
3 TDI input JTAG Test Data Input with internal pullup, latched on the rising edge of TCK.
4 TDO tri_state JTAG Test Data Output with internal pullup, shifted out on the falling edge of TCK; output is a tri-state driver.
5 RST bidirectional Device Reset: open-drain output of the internal VDD monitor, driven low when VDD < VRST and MONEN is high; an external source can force a reset by driving it low.
6 CP1- input Comparator 1 Inverting Input.
7 CP1+ input Comparator 1 Non-Inverting Input.
8 CP0- input Comparator 0 Inverting Input.
9 CP0+ input Comparator 0 Non-Inverting Input.
10 AGND power_in Analog Ground; must be tied to Ground.
11 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
12 VREF power_in Bandgap Voltage Reference Output (all devices).
13 AGND power_in Analog Ground; must be tied to Ground.
14 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
15 NC unconnected No Connection.
16 VREF0 input ADC0 Voltage Reference Input.
17 NC unconnected No Connection.
18 AIN0.0 input ADC0 Input Channel 0.
19 AIN0.1 input ADC0 Input Channel 1.
20 AIN0.2 input ADC0 Input Channel 2.
21 AIN0.3 input ADC0 Input Channel 3.
22 AIN0.4 input ADC0 Input Channel 4.
23 AIN0.5 input ADC0 Input Channel 5.
24 AIN0.6 input ADC0 Input Channel 6.
25 AIN0.7 input ADC0 Input Channel 7.
26 XTAL1 input Crystal Input: return for the internal oscillator circuit for a crystal or ceramic resonator; becomes the system clock if overdriven by an external CMOS clock.
27 XTAL2 output Crystal Output: excitation driver for a crystal or ceramic resonator.
28 MONEN input VDD Monitor Enable: tied high enables the internal VDD monitor, tied low disables it; must be tied high or low.
29 AIN2.7/A15/P1.7 bidirectional Port 1.7, also Bit 15 of the External Memory Address bus in non-multiplexed mode.
30 AIN2.6/A14/P1.6 bidirectional Port 1.6, also Bit 14 of the External Memory Address bus in non-multiplexed mode.
31 AIN2.5/A13/P1.5 bidirectional Port 1.5, also Bit 13 of the External Memory Address bus in non-multiplexed mode.
32 AIN2.4/A12/P1.4 bidirectional Port 1.4, also Bit 12 of the External Memory Address bus in non-multiplexed mode.
33 AIN2.3/A11/P1.3 bidirectional Port 1.3, also Bit 11 of the External Memory Address bus in non-multiplexed mode.
34 AIN2.2/A10/P1.2 bidirectional Port 1.2, also Bit 10 of the External Memory Address bus in non-multiplexed mode.
35 AIN2.1/A9/P1.1 bidirectional Port 1.1, also Bit 9 of the External Memory Address bus in non-multiplexed mode.
36 AIN2.0/A8/P1.0 bidirectional Port 1.0, also Bit 8 of the External Memory Address bus in non-multiplexed mode.
37 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
38 DGND power_in Digital Ground; must be tied to Ground.
39 A15m/A7/P2.7 bidirectional Port 2.7, also External Memory Address bit 15 (multiplexed) or bit 7 (non-multiplexed).
40 A14m/A6/P2.6 bidirectional Port 2.6, also External Memory Address bit 14 (multiplexed) or bit 6 (non-multiplexed).
41 A13m/A5/P2.5 bidirectional Port 2.5, also External Memory Address bit 13 (multiplexed) or bit 5 (non-multiplexed).
42 A12m/A4/P2.4 bidirectional Port 2.4, also External Memory Address bit 12 (multiplexed) or bit 4 (non-multiplexed).
43 A11m/A3/P2.3 bidirectional Port 2.3, also External Memory Address bit 11 (multiplexed) or bit 3 (non-multiplexed).
44 A10m/A2/P2.2 bidirectional Port 2.2, also External Memory Address bit 10 (multiplexed) or bit 2 (non-multiplexed).
45 A9m/A1/P2.1 bidirectional Port 2.1, also External Memory Address bit 9 (multiplexed) or bit 1 (non-multiplexed).
46 A8m/A0/P2.0 bidirectional Port 2.0, also External Memory Address bit 8 (multiplexed) or bit 0 (non-multiplexed).
47 AD7/D7/P3.7 bidirectional Port 3.7, also External Memory Address/Data bit 7 (multiplexed) or Data bit 7 (non-multiplexed).
48 AD6/D6/P3.6 bidirectional Port 3.6, also External Memory Address/Data bit 6 (multiplexed) or Data bit 6 (non-multiplexed).
49 AD5/D5/P3.5 bidirectional Port 3.5, also External Memory Address/Data bit 5 (multiplexed) or Data bit 5 (non-multiplexed).
50 AD4/D4/P3.4 bidirectional Port 3.4, also External Memory Address/Data bit 4 (multiplexed) or Data bit 4 (non-multiplexed).
51 AD3/D3/P3.3 bidirectional Port 3.3, also External Memory Address/Data bit 3 (multiplexed) or Data bit 3 (non-multiplexed).
52 AD2/D2/P3.2 bidirectional Port 3.2, also External Memory Address/Data bit 2 (multiplexed) or Data bit 2 (non-multiplexed).
53 AD1/D1/P3.1 bidirectional Port 3.1, also External Memory Address/Data bit 1 (multiplexed) or Data bit 1 (non-multiplexed).
54 AD0/D0/P3.0 bidirectional Port 3.0, also External Memory Address/Data bit 0 (multiplexed) or Data bit 0 (non-multiplexed).
55 WR/P0.7 bidirectional Port 0.7, also /WR strobe for the External Memory bus.
56 RD/P0.6 bidirectional Port 0.6, also /RD strobe for the External Memory bus.
57 ALE/P0.5 bidirectional Port 0.5, also ALE strobe for the External Memory Address bus in multiplexed mode.
58 P0.4 bidirectional Port 0.4 general-purpose I/O or crossbar-assigned digital function.
59 P0.3 bidirectional Port 0.3 general-purpose I/O or crossbar-assigned digital function.
60 P0.2 bidirectional Port 0.2 general-purpose I/O or crossbar-assigned digital function.
61 P0.1 bidirectional Port 0.1 general-purpose I/O or crossbar-assigned digital function.
62 P0.0 bidirectional Port 0.0 general-purpose I/O or crossbar-assigned digital function.
63 DGND power_in Digital Ground; must be tied to Ground.
64 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
65 AD7/D7/P7.7 bidirectional Port 7.7, also External Memory Address/Data bit 7 (multiplexed) or Data bit 7 (non-multiplexed).
66 AD6/D6/P7.6 bidirectional Port 7.6, also External Memory Address/Data bit 6 (multiplexed) or Data bit 6 (non-multiplexed).
67 AD5/D5/P7.5 bidirectional Port 7.5, also External Memory Address/Data bit 5 (multiplexed) or Data bit 5 (non-multiplexed).
68 AD4/D4/P7.4 bidirectional Port 7.4, also External Memory Address/Data bit 4 (multiplexed) or Data bit 4 (non-multiplexed).
69 AD3/D3/P7.3 bidirectional Port 7.3, also External Memory Address/Data bit 3 (multiplexed) or Data bit 3 (non-multiplexed).
70 AD2/D2/P7.2 bidirectional Port 7.2, also External Memory Address/Data bit 2 (multiplexed) or Data bit 2 (non-multiplexed).
71 AD1/D1/P7.1 bidirectional Port 7.1, also External Memory Address/Data bit 1 (multiplexed) or Data bit 1 (non-multiplexed).
72 AD0/D0/P7.0 bidirectional Port 7.0, also External Memory Address/Data bit 0 (multiplexed) or Data bit 0 (non-multiplexed).
73 A15m/A7/P6.7 bidirectional Port 6.7, also External Memory Address bit 15 (multiplexed) or bit 7 (non-multiplexed).
74 A14m/A6/P6.6 bidirectional Port 6.6, also External Memory Address bit 14 (multiplexed) or bit 6 (non-multiplexed).
75 A13m/A5/P6.5 bidirectional Port 6.5, also External Memory Address bit 13 (multiplexed) or bit 5 (non-multiplexed).
76 A12m/A4/P6.4 bidirectional Port 6.4, also External Memory Address bit 12 (multiplexed) or bit 4 (non-multiplexed).
77 A11m/A3/P6.3 bidirectional Port 6.3, also External Memory Address bit 11 (multiplexed) or bit 3 (non-multiplexed).
78 A10m/A2/P6.2 bidirectional Port 6.2, also External Memory Address bit 10 (multiplexed) or bit 2 (non-multiplexed).
79 A9m/A1/P6.1 bidirectional Port 6.1, also External Memory Address bit 9 (multiplexed) or bit 1 (non-multiplexed).
80 A8m/A0/P6.0 bidirectional Port 6.0, also External Memory Address bit 8 (multiplexed) or bit 0 (non-multiplexed).
81 A15/P5.7 bidirectional Port 5.7, also Bit 15 of the External Memory Address bus in non-multiplexed mode.
82 A14/P5.6 bidirectional Port 5.6, also Bit 14 of the External Memory Address bus in non-multiplexed mode.
83 A13/P5.5 bidirectional Port 5.5, also Bit 13 of the External Memory Address bus in non-multiplexed mode.
84 A12/P5.4 bidirectional Port 5.4, also Bit 12 of the External Memory Address bus in non-multiplexed mode.
85 A11/P5.3 bidirectional Port 5.3, also Bit 11 of the External Memory Address bus in non-multiplexed mode.
86 A10/P5.2 bidirectional Port 5.2, also Bit 10 of the External Memory Address bus in non-multiplexed mode.
87 A9/P5.1 bidirectional Port 5.1, also Bit 9 of the External Memory Address bus in non-multiplexed mode.
88 A8/P5.0 bidirectional Port 5.0, also Bit 8 of the External Memory Address bus in non-multiplexed mode.
89 DGND power_in Digital Ground; must be tied to Ground.
90 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
91 WR/P4.7 bidirectional Port 4.7, also /WR strobe for the External Memory bus.
92 RD/P4.6 bidirectional Port 4.6, also /RD strobe for the External Memory bus.
93 ALE/P4.5 bidirectional Port 4.5, also ALE strobe for the External Memory Address bus in multiplexed mode.
94 P4.4 bidirectional Port 4.4 general-purpose I/O.
95 P4.3 bidirectional Port 4.3 general-purpose I/O.
96 P4.2 bidirectional Port 4.2 general-purpose I/O.
97 P4.1 bidirectional Port 4.1 general-purpose I/O.
98 P4.0 bidirectional Port 4.0 general-purpose I/O.
99 NC unconnected No Connection.
100 NC unconnected No Connection.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 38
Storage Temperature -65 150 °C 38
Voltage on any Pin (except VDD and Port I/O) with respect to DGND -0.3 V max is VDD + 0.3 V 38
Voltage on any Port I/O Pin or RST with respect to DGND -0.3 5.8 V 38
Voltage on VDD with respect to DGND VDD -0.3 4.2 V 38
Maximum Total Current through VDD, AV+, DGND, and AGND 800 mA 38
Maximum Output Current Sunk by any Port pin 100 mA 38
Maximum Output Current Sunk by any other I/O pin 50 mA 38
Maximum Output Current Sourced by any Port pin 100 mA 38
Maximum Output Current Sourced by any other I/O Pin 50 mA 38
Analog Supply Voltage (SYSCLK = 0 to 50 MHz) AV+ 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Analog Supply Voltage (SYSCLK > 50 MHz) AV+ 3 3.3 3.6 V SYSCLK > 50 MHz 39
Analog Supply Current 1.7 mA Internal REF, ADCs, DACs, Comparators all active 39
Analog Supply Current with analog sub-systems inactive 0.2 μA Internal REF, ADCs, DACs, Comparators all disabled, oscillator disabled 39
Analog-to-Digital Supply Delta (/VDD, AV+/) 0.5 V 39
Digital Supply Voltage (SYSCLK = 0 to 50 MHz) VDD 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Digital Supply Voltage (SYSCLK > 50 MHz) VDD 3 3.3 3.6 V SYSCLK > 50 MHz 39
Digital Supply Current with CPU active, 100 MHz 65 mA VDD = 3.0 V, Clock = 100 MHz 39
Digital Supply Current with CPU active, 50 MHz 35 mA VDD = 3.0 V, Clock = 50 MHz 39
Digital Supply Current with CPU active, 1 MHz 1 mA VDD = 3.0 V, Clock = 1 MHz 39
Digital Supply Current with CPU active, 32 kHz 33 μA VDD = 3.0 V, Clock = 32 kHz 39
Digital Supply Current with CPU inactive, 100 MHz 40 mA VDD = 3.0 V, Clock = 100 MHz 39
Digital Supply Current with CPU inactive, 50 MHz 20 mA VDD = 3.0 V, Clock = 50 MHz 39
Digital Supply Current with CPU inactive, 1 MHz 0.4 mA VDD = 3.0 V, Clock = 1 MHz 39
Digital Supply Current with CPU inactive, 32 kHz 15 μA VDD = 3.0 V, Clock = 32 kHz 39
Digital Supply Current (shutdown) 0.4 μA Oscillator not running 39
Digital Supply RAM Data Retention Voltage 1.5 V 39
SYSCLK (System Clock), VDD, AV+ = 2.7 to 3.6 V SYSCLK 0 50 MHz VDD, AV+ = 2.7 to 3.6 V 39
SYSCLK (System Clock), VDD, AV+ = 3.0 to 3.6 V SYSCLK 0 100 MHz VDD, AV+ = 3.0 to 3.6 V 39
Specified Operating Temperature Range -40 85 °C 39
ADC0 Resolution 10 bits 90
ADC0 Integral Nonlinearity INL -1 1 LSB 90
ADC0 Differential Nonlinearity DNL -1 1 LSB Guaranteed Monotonic 90
ADC0 Offset Error 0.5 LSB printed as ±0.5 90
ADC0 Full Scale Error -1.5 LSB Differential mode; printed -1.5±0.5 90
ADC0 Offset Temperature Coefficient 0.25 ppm/°C printed ±0.25 90
ADC0 Signal-to-Noise Plus Distortion SNR 59 dB 10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps 90
ADC0 Total Harmonic Distortion THD -70 dB Up to the 5th harmonic 90
ADC0 Spurious-Free Dynamic Range SFDR 80 dB 90
ADC0 SAR Clock Frequency 2.5 MHz 90
ADC0 Conversion Time in SAR Clocks 16 clocks 90
ADC0 Track/Hold Acquisition Time 1.5 μs 90
ADC0 Throughput Rate 100 ksps 90
ADC0 Input Voltage Range 0 V Single-ended operation; max is VREF 90
ADC0 Power Supply Current (AV+ supplied to ADC) 450 900 μA Operating Mode, 100 ksps 90
Internal Reference Output Voltage VREF 2.36 2.43 2.48 V 25 °C ambient 118
VREF Temperature Coefficient 15 ppm/°C 118
External Reference Input Voltage Range 1 V External Reference (REFBE = 0); max is (AV+), 0.3 118
Comparator Input Offset Voltage -10 10 mV 126
Comparator Input Bias Current -5 0.001 5 nA 126
Comparator Common-Mode Rejection Ratio 1.5 4 mV/V 126
VDD POR Threshold VRST 2.4 2.55 2.7 V 183
Reset Time Delay 80 100 120 ms RST rising edge after VDD crosses VRST threshold 183
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 to 3.6 V 183
Calibrated Internal Oscillator Frequency 24 24.5 25 MHz 185
Flash Erase Cycle Time 10 12 14 ms 200
Flash Write Cycle Time 40 50 60 μs 200
Port I/O Output Low Voltage (IOL = 8.5 mA) VOL 0.6 V IOL = 8.5 mA, VDD = 2.7 to 3.6 V 236

CAD (KiCad official)

  • Symbol: C8051F130-GQ
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: c8051f130-gq-etched.step / c8051f130-gq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f130-gq.step / c8051f130-gq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (350 pp, sha256 de2e31cf5b17be5e, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF