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C8051F120-GQR

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SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F120-GQR

SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-100(14x14)

C8051F120-GQR from SKYWORKS SILICON LABS, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS input JTAG Test Mode Select input with internal pullup.
2 TCK input JTAG Test Clock input with internal pullup.
3 TDI input JTAG Test Data Input with internal pullup, latched on the rising edge of TCK.
4 TDO tri_state JTAG Test Data Output with internal pullup; data is shifted out on the falling edge of TCK and the output is a tri-state driver.
5 RST bidirectional Device Reset: open-drain output of the internal VDD monitor, driven low when VDD is below VRST and MONEN is high; an external source driving it low initiates a system reset.
6 CP1- input Comparator 1 Inverting Input.
7 CP1+ input Comparator 1 Non-Inverting Input.
8 CP0- input Comparator 0 Inverting Input.
9 CP0+ input Comparator 0 Non-Inverting Input.
10 AGND power_in Analog Ground; must be tied to ground.
11 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
12 VREF power_in Bandgap Voltage Reference Output on all devices; the DAC voltage reference input function applies only to C8051F121/3/5/7.
13 AGND power_in Analog Ground; must be tied to ground.
14 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
15 VREFD input DAC Voltage Reference Input.
16 VREF0 input ADC0 Voltage Reference Input.
17 VREF2 input ADC2 Voltage Reference Input.
18 AIN0.0 input ADC0 Input Channel 0 (see ADC0 specification for complete description).
19 AIN0.1 input ADC0 Input Channel 1 (see ADC0 specification for complete description).
20 AIN0.2 input ADC0 Input Channel 2 (see ADC0 specification for complete description).
21 AIN0.3 input ADC0 Input Channel 3 (see ADC0 specification for complete description).
22 AIN0.4 input ADC0 Input Channel 4 (see ADC0 specification for complete description).
23 AIN0.5 input ADC0 Input Channel 5 (see ADC0 specification for complete description).
24 AIN0.6 input ADC0 Input Channel 6 (see ADC0 specification for complete description).
25 AIN0.7 input ADC0 Input Channel 7 (see ADC0 specification for complete description).
26 XTAL1 input Crystal Input: return for the internal oscillator circuit; if overdriven by an external CMOS clock, this pin becomes the system clock.
27 XTAL2 output Crystal Output: excitation driver for a crystal or ceramic resonator.
28 MONEN input VDD Monitor Enable: when tied high it enables the internal VDD monitor, which forces a system reset when VDD is below VRST; it must be tied high or low.
29 AIN2.7/A15/P1.7 bidirectional ADC2 Input Channel 7 (analog input) shared with External Memory Address bit A15 and Port 1.7 digital I/O.
30 AIN2.6/A14/P1.6 bidirectional ADC2 Input Channel 6 (analog input) shared with External Memory Address bit A14 and Port 1.6 digital I/O.
31 AIN2.5/A13/P1.5 bidirectional ADC2 Input Channel 5 (analog input) shared with External Memory Address bit A13 and Port 1.5 digital I/O.
32 AIN2.4/A12/P1.4 bidirectional ADC2 Input Channel 4 (analog input) shared with External Memory Address bit A12 and Port 1.4 digital I/O.
33 AIN2.3/A11/P1.3 bidirectional ADC2 Input Channel 3 (analog input) shared with External Memory Address bit A11 and Port 1.3 digital I/O.
34 AIN2.2/A10/P1.2 bidirectional ADC2 Input Channel 2 (analog input) shared with External Memory Address bit A10 and Port 1.2 digital I/O.
35 AIN2.1/A9/P1.1 bidirectional ADC2 Input Channel 1 (analog input) shared with External Memory Address bit A9 and Port 1.1 digital I/O.
36 AIN2.0/A8/P1.0 bidirectional ADC2 Input Channel 0 (analog input) shared with External Memory Address bit A8 and Port 1.0 digital I/O.
37 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
38 DGND power_in Digital Ground; must be tied to ground.
39 A15m/A7/P2.7 bidirectional Port 2.7 I/O; can be driven by the External Data Memory Interface as Address bit A15 (multiplexed) or A7 (non-multiplexed).
40 A14m/A6/P2.6 bidirectional Port 2.6 I/O; can be driven by the External Data Memory Interface as Address bit A14 (multiplexed) or A6 (non-multiplexed).
41 A13m/A5/P2.5 bidirectional Port 2.5 I/O; can be driven by the External Data Memory Interface as Address bit A13 (multiplexed) or A5 (non-multiplexed).
42 A12m/A4/P2.4 bidirectional Port 2.4 I/O; can be driven by the External Data Memory Interface as Address bit A12 (multiplexed) or A4 (non-multiplexed).
43 A11m/A3/P2.3 bidirectional Port 2.3 I/O; can be driven by the External Data Memory Interface as Address bit A11 (multiplexed) or A3 (non-multiplexed).
44 A10m/A2/P2.2 bidirectional Port 2.2 I/O; can be driven by the External Data Memory Interface as Address bit A10 (multiplexed) or A2 (non-multiplexed).
45 A9m/A1/P2.1 bidirectional Port 2.1 I/O; can be driven by the External Data Memory Interface as Address bit A9 (multiplexed) or A1 (non-multiplexed).
46 A8m/A0/P2.0 bidirectional Port 2.0 I/O; can be driven by the External Data Memory Interface as Address bit A8 (multiplexed) or A0 (non-multiplexed).
47 AD7/D7/P3.7 bidirectional Port 3.7 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD7 (multiplexed) or Data bit D7 (non-multiplexed).
48 AD6/D6/P3.6 bidirectional Port 3.6 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD6 (multiplexed) or Data bit D6 (non-multiplexed).
49 AD5/D5/P3.5 bidirectional Port 3.5 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD5 (multiplexed) or Data bit D5 (non-multiplexed).
50 AD4/D4/P3.4 bidirectional Port 3.4 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD4 (multiplexed) or Data bit D4 (non-multiplexed).
51 AD3/D3/P3.3 bidirectional Port 3.3 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD3 (multiplexed) or Data bit D3 (non-multiplexed).
52 AD2/D2/P3.2 bidirectional Port 3.2 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD2 (multiplexed) or Data bit D2 (non-multiplexed).
53 AD1/D1/P3.1 bidirectional Port 3.1 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD1 (multiplexed) or Data bit D1 (non-multiplexed).
54 AD0/D0/P3.0 bidirectional Port 3.0 I/O; can be driven by the External Data Memory Interface as Address/Data bit AD0 (multiplexed) or Data bit D0 (non-multiplexed).
55 WR/P0.7 bidirectional External Memory Interface /WR strobe or Port 0.7 I/O; the Crossbar skips this pin when EMIFLE is set.
56 RD/P0.6 bidirectional External Memory Interface /RD strobe or Port 0.6 I/O; the Crossbar skips this pin when EMIFLE is set.
57 ALE/P0.5 bidirectional ALE strobe for the External Memory Address bus (multiplexed mode) or Port 0.5 I/O.
58 P0.4 bidirectional Port 0.4 I/O; general-purpose I/O or a digital peripheral pin assigned by the Priority Crossbar Decoder.
59 P0.3 bidirectional Port 0.3 I/O; general-purpose I/O or a digital peripheral pin assigned by the Priority Crossbar Decoder.
60 P0.2 bidirectional Port 0.2 I/O; general-purpose I/O or a digital peripheral pin assigned by the Priority Crossbar Decoder.
61 P0.1 bidirectional Port 0.1 I/O; general-purpose I/O or a digital peripheral pin assigned by the Priority Crossbar Decoder.
62 P0.0 bidirectional Port 0.0 I/O; general-purpose I/O or a digital peripheral pin assigned by the Priority Crossbar Decoder.
63 DGND power_in Digital Ground; must be tied to ground.
64 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
65 AD7/D7/P7.7 bidirectional Port 7.7 I/O; can be driven by the External Data Memory Interface as AD7 (multiplexed) or D7 (non-multiplexed).
66 AD6/D6/P7.6 bidirectional Port 7.6 I/O; can be driven by the External Data Memory Interface as AD6 (multiplexed) or D6 (non-multiplexed).
67 AD5/D5/P7.5 bidirectional Port 7.5 I/O; can be driven by the External Data Memory Interface as AD5 (multiplexed) or D5 (non-multiplexed).
68 AD4/D4/P7.4 bidirectional Port 7.4 I/O; can be driven by the External Data Memory Interface as AD4 (multiplexed) or D4 (non-multiplexed).
69 AD3/D3/P7.3 bidirectional Port 7.3 I/O; can be driven by the External Data Memory Interface as AD3 (multiplexed) or D3 (non-multiplexed).
70 AD2/D2/P7.2 bidirectional Port 7.2 I/O; can be driven by the External Data Memory Interface as AD2 (multiplexed) or D2 (non-multiplexed).
71 AD1/D1/P7.1 bidirectional Port 7.1 I/O; can be driven by the External Data Memory Interface as AD1 (multiplexed) or D1 (non-multiplexed).
72 AD0/D0/P7.0 bidirectional Port 7.0 I/O; can be driven by the External Data Memory Interface as AD0 (multiplexed) or D0 (non-multiplexed).
73 A15m/A7/P6.7 bidirectional Port 6.7 I/O; can be driven by the External Data Memory Interface as Address bit A15 (multiplexed) or A7 (non-multiplexed).
74 A14m/A6/P6.6 bidirectional Port 6.6 I/O; can be driven by the External Data Memory Interface as Address bit A14 (multiplexed) or A6 (non-multiplexed).
75 A13m/A5/P6.5 bidirectional Port 6.5 I/O; can be driven by the External Data Memory Interface as Address bit A13 (multiplexed) or A5 (non-multiplexed).
76 A12m/A4/P6.4 bidirectional Port 6.4 I/O; can be driven by the External Data Memory Interface as Address bit A12 (multiplexed) or A4 (non-multiplexed).
77 A11m/A3/P6.3 bidirectional Port 6.3 I/O; can be driven by the External Data Memory Interface as Address bit A11 (multiplexed) or A3 (non-multiplexed).
78 A10m/A2/P6.2 bidirectional Port 6.2 I/O; can be driven by the External Data Memory Interface as Address bit A10 (multiplexed) or A2 (non-multiplexed).
79 A9m/A1/P6.1 bidirectional Port 6.1 I/O; can be driven by the External Data Memory Interface as Address bit A9 (multiplexed) or A1 (non-multiplexed).
80 A8m/A0/P6.0 bidirectional Port 6.0 I/O; can be driven by the External Data Memory Interface as Address bit A8 (multiplexed) or A0 (non-multiplexed).
81 A15/P5.7 bidirectional Port 5.7 I/O; can be driven by the External Data Memory Interface as Address bit A15 (non-multiplexed mode).
82 A14/P5.6 bidirectional Port 5.6 I/O; can be driven by the External Data Memory Interface as Address bit A14 (non-multiplexed mode).
83 A13/P5.5 bidirectional Port 5.5 I/O; can be driven by the External Data Memory Interface as Address bit A13 (non-multiplexed mode).
84 A12/P5.4 bidirectional Port 5.4 I/O; can be driven by the External Data Memory Interface as Address bit A12 (non-multiplexed mode).
85 A11/P5.3 bidirectional Port 5.3 I/O; can be driven by the External Data Memory Interface as Address bit A11 (non-multiplexed mode).
86 A10/P5.2 bidirectional Port 5.2 I/O; can be driven by the External Data Memory Interface as Address bit A10 (non-multiplexed mode).
87 A9/P5.1 bidirectional Port 5.1 I/O; can be driven by the External Data Memory Interface as Address bit A9 (non-multiplexed mode).
88 A8/P5.0 bidirectional Port 5.0 I/O; can be driven by the External Data Memory Interface as Address bit A8 (non-multiplexed mode).
89 DGND power_in Digital Ground; must be tied to ground.
90 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
91 WR/P4.7 bidirectional External Memory Interface /WR strobe or Port 4.7 I/O; pin is open-drain by default and push-pull when set in P4MDOUT.
92 RD/P4.6 bidirectional External Memory Interface /RD strobe or Port 4.6 I/O; pin is open-drain by default and push-pull when set in P4MDOUT.
93 ALE/P4.5 bidirectional ALE strobe for the External Memory Address bus (multiplexed mode) or Port 4.5 I/O.
94 P4.4 bidirectional Port 4.4 I/O; open-drain by default and push-pull when set in P4MDOUT.
95 P4.3 bidirectional Port 4.3 I/O; open-drain by default and push-pull when set in P4MDOUT.
96 P4.2 bidirectional Port 4.2 I/O; open-drain by default and push-pull when set in P4MDOUT.
97 P4.1 bidirectional Port 4.1 I/O; open-drain by default and push-pull when set in P4MDOUT.
98 P4.0 bidirectional Port 4.0 I/O; open-drain by default and push-pull when set in P4MDOUT.
99 DAC1 output Digital to Analog Converter 1 voltage output (see DAC specification for complete description).
100 DAC0 output Digital to Analog Converter 0 voltage output (see DAC specification for complete description).

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 38
Storage Temperature -65 150 °C 38
Voltage on any Port I/O Pin or RST with Respect to DGND -0.3 5.8 V 38
Voltage on VDD with Respect to DGND -0.3 4.2 V 38
Voltage on any pin (except VDD and Port I/O) with Respect to DGND -0.3 V 38
Maximum Total Current through VDD, AV+, DGND, and AGND 800 mA 38
Maximum Output Current Sunk by any Port pin 100 mA 38
Maximum Output Current Sunk by any other I/O pin 50 mA 38
Maximum Output Current Sourced by any Port pin 100 mA 38
Maximum Output Current Sourced by any other I/O pin 50 mA 38
Analog Supply Voltage 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Analog Supply Voltage 3 3.3 3.6 V SYSCLK > 50 MHz 39
Digital Supply Voltage 2.7 3 3.6 V SYSCLK = 0 to 50 MHz 39
Digital Supply Voltage 3 3.3 3.6 V SYSCLK > 50 MHz 39
Analog-to-Digital Supply Delta (/VDD, AV+/) 0.5 V 39
SYSCLK (System Clock) 0 50 MHz VDD, AV+ = 2.7 to 3.6 V 39
SYSCLK (System Clock) 0 100 MHz VDD, AV+ = 3.0 to 3.6 V 39
Specified Operating Temperature Range -40 85 °C 39
RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 to 3.6 V 183
VDD for RST Output Valid 1 V 183
AV+ for RST Output Valid 1 V 183
VDD POR Threshold (VRST) VRST 2.4 2.55 2.7 V 183
Minimum RST Low Time to Generate a System Reset 10 ns 183
Reset Time Delay 80 100 120 ms RST rising edge after VDD crosses VRST threshold 183
Missing Clock Detector Timeout 100 220 500 µs from last system clock to reset initiation 183
Calibrated Internal Oscillator Frequency 24 24.5 25 MHz 185
External Clock Frequency 0 30 MHz 185
TXCH (External Clock High Time) TXCH 15 ns 185
TXCL (External Clock Low Time) TXCL 15 ns 185
Input Frequency (Divided Reference Frequency) 5 30 MHz 195
PLL Output Frequency 25 100 MHz 195
Output Voltage 2.36 2.43 2.48 V 25 °C ambient 118
VREF Short-Circuit Current VREF 30 mA 118
External Reference Input Voltage Range 1 V External Reference (REFBE = 0) 118
External Reference Input Current 0 1 µA External Reference (REFBE = 0) 118
Integral Nonlinearity (12-bit ADC0) -1 1 LSB 72
Differential Nonlinearity (12-bit ADC0) -1 1 LSB Guaranteed Monotonic 72
Offset Error (12-bit ADC0) -1 -3 1 LSB 72
Full Scale Error (12-bit ADC0) -3 -7 3 LSB Differential mode 72
Signal-to-Noise Plus Distortion (12-bit ADC0) 66 dB 10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps 72
SAR Clock Frequency (12-bit ADC0) 2.5 MHz 72
Conversion Time in SAR Clocks (12-bit ADC0) 16 clocks 72
Track/Hold Acquisition Time (12-bit ADC0) 1.5 µs 72
Throughput Rate (12-bit ADC0) 100 ksps 72
Power Supply Current (AV+ supplied to 12-bit ADC0) 450 900 µA Operating Mode, 100 ksps 72
Integral Nonlinearity (8-bit ADC2) -1 1 LSB 103
Differential Nonlinearity (8-bit ADC2) -1 1 LSB Guaranteed Monotonic 103
Signal-to-Noise Plus Distortion (8-bit ADC2) 45 47 dB 10 kHz sine-wave input, 1 dB below Full Scale, 500 ksps 103
Throughput Rate (8-bit ADC2) 500 ksps 103
Power Supply Current (AV+ supplied to ADC2) 420 900 µA Operating Mode, 500 ksps 103
Integral Nonlinearity (12-bit DAC) -1.5 1.5 LSB 111
Differential Nonlinearity (12-bit DAC) -1 1 LSB 111
Offset Error (DAC) -30 30 mV Data Word = 0x014 111
Full-Scale Error (DAC) -60 60 mV 111
Output Voltage Swing (DAC) 0 V 111
Power Supply Current (AV+ supplied to DAC) 110 400 µA Data Word = 0x7FF 111
Input Bias Current (Comparator) -5 0.001 5 nA 126
Input Offset Voltage (Comparator) -10 10 mV 126
Inverting or Non-Inverting Input Voltage Range (Comparator) -0.25 V 126
Common-Mode Rejection Ratio (Comparator) 1.5 4 mV/V 126

CAD (KiCad official)

  • Symbol: C8051F120-GQR
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: c8051f120-gqr-etched.step / c8051f120-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f120-gqr.step / c8051f120-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (350 pp, sha256 24fdae17f6f8efe6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF