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C8051F060-GQ

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerc8051f060-gqfactory-2.0.0extractor-text

Changed since verified C8051F060-GQ

by Ray · last 31 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 100 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F060-GQ · TQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 330-page datasheet
  • ✓distributor: lcsc C3235947, digikey 336-1213-ND, mouser 634-C8051F060-GQ
  • ✓family: TQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5tcjl3k3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! c8051f060-gq.kicad_sym✓ c8051f060-gq.kicad_mod✓ c8051f060-gq.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers c8051f060-gq: symbol repaired (body fitted to the names) · Ray
c8051f060-gq-etched.glb Publish 0.1.0 · Ray
c8051f060-gq-etched.step c8051f060-gq: factory component page (tier=lcsc) · Ray
c8051f060-gq-hero.glb c8051f060-gq: hero GLB from the etched model (keeps the MPN mark) · Ray
c8051f060-gq-hero.overlay.json Publish 0.1.0 · Ray
c8051f060-gq.glb Publish 0.1.0 · Ray
c8051f060-gq.kicad_mod Publish 0.1.0 · Ray
c8051f060-gq.kicad_sym c8051f060-gq: symbol repaired (body fitted to the names) · Ray
c8051f060-gq.lbr c8051f060-gq: symbol repaired (body fitted to the names) · Ray
c8051f060-gq.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 100 pins · Ray

C8051F060-GQ

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(14x14)

C8051F060-GQ from SILICON LABS, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DAC1 output Digital to Analog Converter 1 voltage output.
2 VREF2 input ADC2 Voltage Reference Input.
3 VREFD input DAC0 and DAC1 Voltage Reference Input.
4 VREF power_in Bandgap Voltage Reference Output.
5 VBGAP1 output ADC1 Bandgap Bypass Pin.
6 VREF1 bidirectional Bandgap Voltage Reference Output for ADC1 and ADC1 Voltage Reference Input.
7 VRGND1 input ADC1 Voltage Reference Ground; should be grounded if using the ADC.
8 AIN1G input ADC1 DC Bias Input.
9 AIN1 input ADC1 Signal Input.
10 AGND power_in Analog Ground; must be tied to Ground.
11 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
12 CNVSTR1 input External Conversion Start Source for ADC1.
13 AVDD power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
14 AGND power_in Analog Ground; must be tied to Ground.
15 CNVSTR0 input External Conversion Start Source for ADC0.
16 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
17 AGND power_in Analog Ground; must be tied to Ground.
18 AIN0 input ADC0 Signal Input.
19 AIN0G input ADC0 DC Bias Input.
20 VRGND0 input ADC0 Voltage Reference Ground; should be grounded if using the ADC.
21 VREF0 bidirectional Bandgap Voltage Reference Output for ADC0 and ADC0 Voltage Reference Input.
22 VBGAP0 output ADC0 Bandgap Bypass Pin.
23 AGND power_in Analog Ground; must be tied to Ground.
24 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
25 DAC0 output Digital to Analog Converter 0 voltage output.
26 XTAL1 input Crystal Input; return for the internal oscillator circuit, becomes the system clock if overdriven by an external CMOS clock.
27 XTAL2 output Crystal Output; excitation driver for a crystal or ceramic resonator.
28 MONEN input VDD Monitor Enable; tied high enables the monitor that resets when VDD < 2.7 V, recommended connected directly to VDD.
29 P1.7/AIN2.7 bidirectional Port 1.7 general-purpose I/O or ADC2 input channel 7.
30 P1.6/AIN2.6 bidirectional Port 1.6 general-purpose I/O or ADC2 input channel 6.
31 P1.5/AIN2.5 bidirectional Port 1.5 general-purpose I/O or ADC2 input channel 5.
32 P1.4/AIN2.4 bidirectional Port 1.4 general-purpose I/O or ADC2 input channel 4.
33 P1.3/AIN2.3 bidirectional Port 1.3 general-purpose I/O or ADC2 input channel 3.
34 P1.2/AIN2.2 bidirectional Port 1.2 general-purpose I/O or ADC2 input channel 2.
35 P1.1/AIN2.1 bidirectional Port 1.1 general-purpose I/O or ADC2 input channel 1.
36 P1.0/AIN2.0 bidirectional Port 1.0 general-purpose I/O or ADC2 input channel 0.
37 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
38 DGND power_in Digital Ground; must be tied to Ground.
39 P2.7 bidirectional Port 2.7 general-purpose I/O.
40 P2.6 bidirectional Port 2.6 general-purpose I/O.
41 P2.5 bidirectional Port 2.5 general-purpose I/O.
42 P2.4 bidirectional Port 2.4 general-purpose I/O.
43 P2.3 bidirectional Port 2.3 general-purpose I/O.
44 P2.2 bidirectional Port 2.2 general-purpose I/O.
45 P2.1 bidirectional Port 2.1 general-purpose I/O.
46 P2.0 bidirectional Port 2.0 general-purpose I/O.
47 P3.7 bidirectional Port 3.7 general-purpose I/O.
48 P3.6 bidirectional Port 3.6 general-purpose I/O.
49 P3.5 bidirectional Port 3.5 general-purpose I/O.
50 P3.4 bidirectional Port 3.4 general-purpose I/O.
51 P3.3 bidirectional Port 3.3 general-purpose I/O.
52 P3.2 bidirectional Port 3.2 general-purpose I/O.
53 P3.1 bidirectional Port 3.1 general-purpose I/O.
54 P3.0 bidirectional Port 3.0 general-purpose I/O.
55 P0.7 bidirectional Port 0.7 general-purpose I/O.
56 P0.6 bidirectional Port 0.6 general-purpose I/O.
57 P0.5 bidirectional Port 0.5 general-purpose I/O.
58 P0.4 bidirectional Port 0.4 general-purpose I/O.
59 P0.3 bidirectional Port 0.3 general-purpose I/O.
60 P0.2 bidirectional Port 0.2 general-purpose I/O.
61 P0.1 bidirectional Port 0.1 general-purpose I/O.
62 P0.0 bidirectional Port 0.0 general-purpose I/O.
63 DGND power_in Digital Ground; must be tied to Ground.
64 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
65 P7.7/AD7m/D7 bidirectional Port 7.7 I/O or bit 7 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
66 P7.6/AD6m/D6 bidirectional Port 7.6 I/O or bit 6 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
67 P7.5/AD5m/D5 bidirectional Port 7.5 I/O or bit 5 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
68 P7.4/AD4m/D4 bidirectional Port 7.4 I/O or bit 4 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
69 P7.3/AD3m/D3 bidirectional Port 7.3 I/O or bit 3 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
70 P7.2/AD2m/D2 bidirectional Port 7.2 I/O or bit 2 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
71 P7.1/AD1m/D1 bidirectional Port 7.1 I/O or bit 1 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
72 P7.0/AD0m/D0 bidirectional Port 7.0 I/O or bit 0 of the external memory address/data bus (multiplexed) or data bus (non-multiplexed).
73 P6.7/A15m/A7 bidirectional Port 6.7 I/O or external memory address bit 15 (multiplexed) or bit 7 (non-multiplexed).
74 P6.6/A14m/A6 bidirectional Port 6.6 I/O or external memory address bit 14 (multiplexed) or bit 6 (non-multiplexed).
75 P6.5/A13m/A5 bidirectional Port 6.5 I/O or external memory address bit 13 (multiplexed) or bit 5 (non-multiplexed).
76 P6.4/A12m/A4 bidirectional Port 6.4 I/O or external memory address bit 12 (multiplexed) or bit 4 (non-multiplexed).
77 P6.3/A11m/A3 bidirectional Port 6.3 I/O or external memory address bit 11 (multiplexed) or bit 3 (non-multiplexed).
78 P6.2/A10m/A2 bidirectional Port 6.2 I/O or external memory address bit 10 (multiplexed) or bit 2 (non-multiplexed).
79 P6.1/A9m/A1 bidirectional Port 6.1 I/O or external memory address bit 9 (multiplexed) or bit 1 (non-multiplexed).
80 P6.0/A8m/A0 bidirectional Port 6.0 I/O or external memory address bit 8 (multiplexed) or bit 0 (non-multiplexed).
81 P5.7/A15 bidirectional Port 5.7 I/O or bit 15 of the external memory address bus (non-multiplexed mode).
82 P5.6/A14 bidirectional Port 5.6 I/O or bit 14 of the external memory address bus (non-multiplexed mode).
83 P5.5/A13 bidirectional Port 5.5 I/O or bit 13 of the external memory address bus (non-multiplexed mode).
84 P5.4/A12 bidirectional Port 5.4 I/O or bit 12 of the external memory address bus (non-multiplexed mode).
85 P5.3/A11 bidirectional Port 5.3 I/O or bit 11 of the external memory address bus (non-multiplexed mode).
86 P5.2/A10 bidirectional Port 5.2 I/O or bit 10 of the external memory address bus (non-multiplexed mode).
87 P5.1/A9 bidirectional Port 5.1 I/O or bit 9 of the external memory address bus (non-multiplexed mode).
88 P5.0/A8 bidirectional Port 5.0 I/O or bit 8 of the external memory address bus (non-multiplexed mode).
89 DGND power_in Digital Ground; must be tied to Ground.
90 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
91 P4.7/WR bidirectional Port 4.7 I/O or /WR strobe for the external memory address bus.
92 P4.6/RD bidirectional Port 4.6 I/O or /RD strobe for the external memory address bus.
93 P4.5/ALE bidirectional Port 4.5 I/O or ALE strobe for the external memory address bus (multiplexed mode).
94 CANTX output Controller Area Network transmit output.
95 CANRX input Controller Area Network receive input.
96 TMS input JTAG Test Mode Select with internal pull-up.
97 TCK input JTAG Test Clock with internal pull-up.
98 TDI input JTAG Test Data Input with internal pull-up, latched on the rising edge of TCK.
99 TDO tri_state JTAG Test Data Output with internal pull-up, shifted out on the falling edge of TCK, tri-state driver.
100 /RST bidirectional Device Reset; open-drain output of the VDD monitor driven low when VDD < 2.7 V and MONEN is high, and an external low initiates a system reset.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 38
Storage temperature -65 150 °C 38
Voltage on any Port 0 pin wrt DGND -0.3 5.8 V 38
Voltage on VDD, AV+ or AVDD wrt DGND -0.3 4.2 V 38
Maximum total current through VDD, AV+, AVDD, DGND, AGND 800 mA 38
Maximum output current sunk by any Port pin 100 mA 38
Maximum output current sunk by any other I/O pin 50 mA 38
Maximum output current sourced by any Port pin 100 mA 38
Maximum output current sourced by any other I/O pin 50 mA 38
Analog Supply Voltage AV+, AVDD 2.7 3 3.6 V -40 to +85 °C, 25 MHz system clock 39
Digital Supply Voltage VDD 2.7 3 3.6 V 39
Analog-to-Digital Supply Delta /VDD - AV+/ 0.5 V 39
Supply Current from Analog Peripherals (active) 14 mA Internal REF, ADC, DAC, Comparators all enabled 39
Supply Current from Analog Peripherals (inactive) 0.2 µA Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled 39
Supply current, CPU active 20 mA VDD=3.0 V, Clock=25 MHz 39
Supply current, CPU inactive 16 mA VDD=3.0 V, Clock=25 MHz, not accessing Flash 39
Supply Current with all systems shut down 0.2 µA Oscillator not running 39
VDD Supply RAM Data Retention Voltage 1.5 V 39
System Clock SYSCLK 0 25 MHz 39
Specified Operating Temperature Range -40 85 °C 39
16-bit ADC Resolution 16 bits 75
16-bit ADC INL, single-ended INL 0.75 2 LSB Single-Ended (C8051F060/1/4/5/6/7 column) 75
16-bit ADC INL, differential INL 0.5 1 LSB Differential (C8051F060/1/4/5/6/7 column) 75
16-bit ADC DNL DNL 0.5 LSB Guaranteed Monotonic 75
16-bit ADC Gain Temperature Coefficient 0.5 ppm/°C 75
16-bit ADC SAR Clock Frequency 25 MHz 75
16-bit ADC Track/Hold Acquisition Time 280 ns 75
16-bit ADC Throughput Rate 1 Msps 75
16-bit ADC Input Voltage Range, single-ended 0 V Single-Ended (AINn - AINnG); upper limit printed as VREF 75
16-bit ADC Input Capacitance 80 pF 75
16-bit ADC Operating Input Range AIN0 or AIN1 -0.2 V upper limit printed as AV+ 76
16-bit ADC Operating Input Range AIN0G or AIN1G -0.2 0.6 V DC Only 76
VREF0/1 Internal Reference Output Voltage 2.36 2.43 2.48 V 25 °C ambient 76
VREF0/1 Temperature Coefficient 15 ppm/°C 76
VREF0/1 External Reference Input Voltage Range 2 V upper limit printed as AV+ 76
ADC2 INL INL 0.5 1 LSB 103
ADC2 DNL DNL 0.5 1 LSB Guaranteed Monotonic 103
ADC2 Offset Error -12 1 12 LSB 103
ADC2 Full Scale Error -15 -5 5 LSB Differential mode 103
ADC2 Signal-to-Noise Plus Distortion 53 55.5 dB 10 kHz sine-wave differential input, 1 dB below full scale, 200 ksps 103
ADC2 SAR Conversion Clock 3 MHz 103
ADC2 Track/Hold Acquisition Time 300 ns 103
ADC2 Throughput Rate 200 ksps 103
ADC2 Power Supply Current 400 900 µA Operating Mode, 200 ksps 103
ADC2 Temperature Sensor Offset Error 8.9 mV Temp = 0 °C, one standard deviation, printed ± 103
DAC Integral Nonlinearity INL 1.5 LSB printed ±1.5 111
DAC Offset Error 3 30 mV Data Word = 0x014, printed ± 111
DAC Full-Scale Error 20 60 mV printed ± 111
DAC Power Supply Current (each DAC) 300 500 µA Data Word = 0x7FF 111
VREF2 Internal Reference Output Voltage 2.36 2.43 2.48 V 25 °C ambient, REFBE = 1 114
VREF2 External Reference Input Voltage Range 1 V REFBE = 0; upper limit printed as (AV+) - 0.3 114
Comparator Positive Hysteresis 2 3 5 7 mV CPnHYP1-0 = 01 124
Comparator Positive Hysteresis 4 15 20 25 mV CPnHYP1-0 = 11 124
Comparator Input Offset Voltage -5 5 mV 124
VDD POR Threshold VRST 2.4 2.55 2.7 V 171
Reset Time Delay 80 100 120 ms /RST rising edge after VDD crosses VRST threshold 171
Calibrated Internal Oscillator Frequency 24 24.5 25 MHz -40°C to +85°C 175
Flash Erase Cycle Time 10 12 14 ms 180

CAD (KiCad official)

  • Symbol: C8051F060-GQ
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: c8051f060-gq-etched.step / c8051f060-gq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f060-gq.step / c8051f060-gq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (330 pp, sha256 b13caf1e0bcedae1, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF