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C8051F041-GQR

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SILICON LABS SILICON LABS, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F041-GQR

SILICON LABS · SILICON LABS · TQFP-64(10x10)

C8051F041-GQR from SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CANRX input Controller Area Network receive input.
2 CANTX output Controller Area Network transmit output.
3 AV+ power_in Analog supply voltage, must be tied to +2.7 to +3.6 V.
4 AGND power_in Analog ground, must be tied to ground.
5 AGND power_in Analog ground, must be tied to ground.
6 AV+ power_in Analog supply voltage, must be tied to +2.7 to +3.6 V.
7 VREF power_in Bandgap voltage reference output; also DAC voltage reference input on the C8051F041/3.
8 VREFA input ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only) voltage reference input.
9 AIN0.0 input ADC0 input channel 0.
10 AIN0.1 input ADC0 input channel 1.
11 AIN0.2 input ADC0 input channel 2.
12 AIN0.3 input ADC0 input channel 3.
13 HVCAP bidirectional High voltage difference amplifier capacitor pin.
14 HVREF input High voltage difference amplifier bias reference.
15 HVAIN+ input High voltage difference amplifier positive signal input.
16 HVAIN- input High voltage difference amplifier negative signal input.
17 XTAL1 input Crystal input, return for the internal oscillator circuit; becomes the system clock if overdriven by an external CMOS clock.
18 XTAL2 output Crystal output, excitation driver for a crystal or ceramic resonator.
19 MONEN input VDD monitor enable; tied high enables the monitor that resets when VDD < 2.7 V, tied low disables it, normally connected directly to VDD.
20 P1.7/AIN2.7/A15 bidirectional Port 1.7, ADC2 input AIN2.7 or external memory address bit 15 (non-multiplexed mode).
21 P1.6/AIN2.6/A14 bidirectional Port 1.6, ADC2 input AIN2.6 or external memory address bit 14 (non-multiplexed mode).
22 P1.5/AIN2.5/A13 bidirectional Port 1.5, ADC2 input AIN2.5 or external memory address bit 13 (non-multiplexed mode).
23 P1.4/AIN2.4/A12 bidirectional Port 1.4, ADC2 input AIN2.4 or external memory address bit 12 (non-multiplexed mode).
24 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
25 DGND power_in Digital ground, must be tied to ground.
26 P1.3/AIN2.3/A11 bidirectional Port 1.3, ADC2 input AIN2.3 or external memory address bit 11 (non-multiplexed mode).
27 P1.2/AIN2.2/A10 bidirectional Port 1.2, ADC2 input AIN2.2 or external memory address bit 10 (non-multiplexed mode).
28 P1.1/AIN2.1/A9 bidirectional Port 1.1, ADC2 input AIN2.1 or external memory address bit 9 (non-multiplexed mode).
29 P1.0/AIN2.0/A8 bidirectional Port 1.0, ADC2 input AIN2.0 or external memory address bit 8 (non-multiplexed mode).
30 P2.7/A15m/A7 bidirectional Port 2.7, external memory address bit 15 (multiplexed mode) or bit 7 (non-multiplexed mode).
31 P2.6/A14m/A6 bidirectional Port 2.6, external memory address bit 14 (multiplexed mode) or bit 6 (non-multiplexed mode).
32 P2.5/A13m/A5 bidirectional Port 2.5, external memory address bit 13 (multiplexed mode) or bit 5 (non-multiplexed mode).
33 P2.4/A12m/A4 bidirectional Port 2.4, external memory address bit 12 (multiplexed mode) or bit 4 (non-multiplexed mode).
34 P2.3/A11m/A3 bidirectional Port 2.3, external memory address bit 11 (multiplexed mode) or bit 3 (non-multiplexed mode).
35 P2.2/A10m/A2 bidirectional Port 2.2, external memory address bit 10 (multiplexed mode) or bit 2 (non-multiplexed mode).
36 P2.1/A9m/A1 bidirectional Port 2.1, external memory address bit 9 (multiplexed mode) or bit 1 (non-multiplexed mode).
37 P2.0/A8m/A0 bidirectional Port 2.0, external memory address bit 8 (multiplexed mode) or bit 0 (non-multiplexed mode).
38 P3.7/AD7/D7 bidirectional Port 3.7, external memory address/data bit 7 (multiplexed) or data bit 7 (non-multiplexed); also ADC0 input.
39 P3.6/AD6/D6 bidirectional Port 3.6, external memory address/data bit 6 (multiplexed) or data bit 6 (non-multiplexed); also ADC0 input.
40 DGND power_in Digital ground, must be tied to ground.
41 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
42 P3.5/AD5/D5 bidirectional Port 3.5, external memory address/data bit 5 (multiplexed) or data bit 5 (non-multiplexed); also ADC0 input.
43 P3.4/AD4/D4 bidirectional Port 3.4, external memory address/data bit 4 (multiplexed) or data bit 4 (non-multiplexed); also ADC0 input.
44 P3.3/AD3/D3 bidirectional Port 3.3, external memory address/data bit 3 (multiplexed) or data bit 3 (non-multiplexed); also ADC0 input.
45 P3.2/AD2/D2 bidirectional Port 3.2, external memory address/data bit 2 (multiplexed) or data bit 2 (non-multiplexed); also ADC0 input.
46 P3.1/AD1/D1 bidirectional Port 3.1, external memory address/data bit 1 (multiplexed) or data bit 1 (non-multiplexed); also ADC0 input.
47 P3.0/AD0/D0 bidirectional Port 3.0, external memory address/data bit 0 (multiplexed) or data bit 0 (non-multiplexed); also ADC0 input.
48 P0.7/WR bidirectional Port 0.7 or /WR strobe for the external memory bus.
49 P0.6/RD bidirectional Port 0.6 or /RD strobe for the external memory bus.
50 P0.5/ALE bidirectional Port 0.5 or ALE strobe for the external memory address bus (multiplexed mode).
51 P0.4 bidirectional Port 0.4 general-purpose I/O.
52 P0.3 bidirectional Port 0.3 general-purpose I/O.
53 P0.2 bidirectional Port 0.2 general-purpose I/O.
54 P0.1 bidirectional Port 0.1 general-purpose I/O.
55 P0.0 bidirectional Port 0.0 general-purpose I/O.
56 DGND power_in Digital ground, must be tied to ground.
57 VDD power_in Digital supply voltage, must be tied to +2.7 to +3.6 V.
58 TMS input JTAG test mode select with internal pullup.
59 TCK input JTAG test clock with internal pullup.
60 TDI input JTAG test data input with internal pullup, latched on the rising edge of TCK.
61 TDO tri_state JTAG test data output with internal pullup, shifted out on the falling edge of TCK, tri-state driver.
62 /RST bidirectional Device reset; open-drain output of the internal VDD monitor driven low when VDD < 2.7 V and MONEN is high, and an external source can reset the system by driving it low.
63 DAC1 output Digital to analog converter 1 voltage output (C8051F040/1/2/3 only).
64 DAC0 output Digital to analog converter 0 voltage output (C8051F040/1/2/3 only).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 35
Storage temperature -65 150 °C 35
Voltage on VDD with respect to DGND VDD -0.3 4.2 V 35
Voltage on any Port I/O pin, /RST, JTAG pins -0.3 5.8 V with respect to DGND 35
Maximum total current through VDD, AV+, DGND, AGND 800 mA 35
Maximum output current sunk by any Port pin 100 mA 35
Maximum output current sunk by any other I/O pin 50 mA 35
Maximum output current sourced by any Port pin 100 mA 35
Maximum output current sourced by any other I/O pin 50 mA 35
Analog supply voltage AV+ 2.7 3 3.6 V 36
Digital supply voltage VDD 2.7 3 3.6 V 36
Analog-to-digital supply delta /VDD - AV+/ 0.5 V 36
Specified operating temperature range -40 85 °C 36
System clock frequency SYSCLK 0 25 MHz 36
SYSCLK low time Tsysl 18 ns 36
SYSCLK high time Tsysh 18 ns 36
Digital supply current, CPU active 10 mA VDD = 2.7 V, Clock = 25 MHz 36
Digital supply current, CPU inactive (Idle) 5 mA VDD = 2.7 V, Clock = 25 MHz 36
Digital supply RAM data retention voltage 1.5 V 36
12-bit ADC resolution 12 bits 67
12-bit ADC integral nonlinearity INL -1 1 LSB 67
12-bit ADC differential nonlinearity DNL -1 1 LSB Guaranteed Monotonic 67
12-bit ADC signal-to-noise plus distortion 66 dB 10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps 67
12-bit ADC SAR clock frequency 2.5 MHz 67
12-bit ADC conversion time 16 clocks in SAR clocks 67
12-bit ADC track/hold acquisition time 1.5 μs 67
12-bit ADC throughput rate 100 ksps 67
12-bit ADC input voltage range 0 V Single-ended operation, 0 to VREF 67
12-bit ADC power supply current 450 900 μA Operating Mode, 100 ksps 67
HV difference amp differential range peak-to-peak 60 V 68
HV difference amp common mode range -60 60 V (HVAIN+), (HVAIN-) = 0 V 68
HV difference amp output voltage range 0.1 2.9 V 68
HV difference amp common mode rejection ratio CMRR 44 52 dB Vcm = -10 V to +10 V, Rs=0 68
HV difference amp quiescent current 450 1000 μA 68
ADC2 resolution 8 bits 103
ADC2 integral nonlinearity INL -1 1 LSB 103
ADC2 differential nonlinearity DNL -1 1 LSB Guaranteed Monotonic 103
ADC2 signal-to-noise plus distortion 45 47 dB 10 kHz sine-wave input, 0 to 1 dB below Full Scale, 500 ksps 103
ADC2 SAR conversion clock frequency 6 MHz 103
ADC2 throughput rate 500 ksps 103
ADC2 power supply current 420 900 μA Operating Mode, 500 ksps 103
DAC resolution 12 bits 110
DAC offset error 3 30 mV Data Word = 0x014 110
DAC full-scale error 20 60 mV 110
DAC power supply current (each DAC) 110 400 μA Data Word = 0x7FF 110
Internal reference output voltage VREF 2.36 2.43 2.48 V 25 °C ambient 116
VREF short-circuit current 30 mA 116
VREF temperature coefficient 15 ppm/°C 116
External reference input voltage range 1 V REFBE = 0, upper limit (AV+), 0.3 V 116
External reference input current 0 1 μA REFBE = 0 116
Comparator input offset voltage -5 5 mV 122
Comparator input bias current -5 0.001 5 nA 122
Comparator input voltage range -0.25 V upper limit VDD + 0.25 V 122
/RST output low voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 167
VDD POR threshold VRST 2.4 2.55 2.7 V 167
Reset time delay 80 100 120 ms RST rising edge after VDD crosses VRST threshold 167
Calibrated internal oscillator frequency 24 24.5 25 MHz 170
Flash erase cycle time 10 12 14 ms 176
Flash write cycle time 40 50 60 μs 176
Port I/O output low voltage VOL 0.6 V IOL = 8.5 mA 198
Port I/O output low voltage VOL 0.1 V IOL = 10 μA 198

CAD (KiCad official)

  • Symbol: C8051F041-GQR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: c8051f041-gqr-etched.step / c8051f041-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f041-gqr.step / c8051f041-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (320 pp, sha256 621ee880b8abd78a, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF