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C8051F022-GQR

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SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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C8051F022-GQR

SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-100(14x14)

C8051F022-GQR from SKYWORKS SILICON LABS, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS input JTAG Test Mode Select with internal pull-up.
2 TCK input JTAG Test Clock with internal pull-up.
3 TDI input JTAG Test Data Input with internal pull-up; TDI is latched on the rising edge of TCK.
4 TDO tri_state JTAG Test Data Output with internal pull-up; data is shifted out on TDO on the falling edge of TCK and TDO is a tri-state driver.
5 /RST bidirectional Device Reset: open-drain output of the internal VDD monitor, driven low when VDD is below 2.7 V and MONEN is high; an external source can initiate a system reset by driving this pin low.
6 CP1- input Comparator 1 inverting input.
7 CP1+ input Comparator 1 non-inverting input.
8 CP0- input Comparator 0 inverting input.
9 CP0+ input Comparator 0 non-inverting input.
10 AGND power_in Analog Ground; must be tied to ground.
11 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
12 VREF power_in Bandgap Voltage Reference Output (all devices); on this package the DAC voltage reference input function is not available (F021/F023 only).
13 AGND power_in Analog Ground; must be tied to ground.
14 AV+ power_in Analog Supply Voltage; must be tied to +2.7 to +3.6 V.
15 VREFD input DAC Voltage Reference Input.
16 VREF0 input ADC0 Voltage Reference Input.
17 VREF1 input ADC1 Voltage Reference Input.
18 AIN0.0 input ADC0 Input Channel 0 (see ADC0 specification).
19 AIN0.1 input ADC0 Input Channel 1 (see ADC0 specification).
20 AIN0.2 input ADC0 Input Channel 2 (see ADC0 specification).
21 AIN0.3 input ADC0 Input Channel 3 (see ADC0 specification).
22 AIN0.4 input ADC0 Input Channel 4 (see ADC0 specification).
23 AIN0.5 input ADC0 Input Channel 5 (see ADC0 specification).
24 AIN0.6 input ADC0 Input Channel 6 (see ADC0 specification).
25 AIN0.7 input ADC0 Input Channel 7 (see ADC0 specification).
26 XTAL1 input Crystal Input: return for the internal oscillator with a crystal or ceramic resonator; if overdriven by an external CMOS clock, this pin becomes the system clock.
27 XTAL2 output Crystal Output: excitation driver for a crystal or ceramic resonator.
28 MONEN input VDD Monitor Enable: when tied high the internal VDD monitor is enabled and forces a system reset when VDD is below 2.7 V; when tied low it is disabled.
29 AIN1.7/A15/P1.7 bidirectional Port 1.7 digital I/O, or ADC1 analog input AIN1.7 when P1MDIN.7 is 0; also external memory address bit 15 in non-multiplexed mode.
30 AIN1.6/A14/P1.6 bidirectional Port 1.6 digital I/O, or ADC1 analog input AIN1.6 when P1MDIN.6 is 0; also external memory address bit 14 in non-multiplexed mode.
31 AIN1.5/A13/P1.5 bidirectional Port 1.5 digital I/O, or ADC1 analog input AIN1.5 when P1MDIN.5 is 0; also external memory address bit 13 in non-multiplexed mode.
32 AIN1.4/A12/P1.4 bidirectional Port 1.4 digital I/O, or ADC1 analog input AIN1.4 when P1MDIN.4 is 0; also external memory address bit 12 in non-multiplexed mode.
33 AIN1.3/A11/P1.3 bidirectional Port 1.3 digital I/O, or ADC1 analog input AIN1.3 when P1MDIN.3 is 0; also external memory address bit 11 in non-multiplexed mode.
34 AIN1.2/A10/P1.2 bidirectional Port 1.2 digital I/O, or ADC1 analog input AIN1.2 when P1MDIN.2 is 0; also external memory address bit 10 in non-multiplexed mode.
35 AIN1.1/A9/P1.1 bidirectional Port 1.1 digital I/O, or ADC1 analog input AIN1.1 when P1MDIN.1 is 0; also external memory address bit 9 in non-multiplexed mode.
36 AIN1.0/A8/P1.0 bidirectional Port 1.0 digital I/O, or ADC1 analog input AIN1.0 when P1MDIN.0 is 0; also external memory address bit 8 in non-multiplexed mode.
37 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
38 DGND power_in Digital Ground; must be tied to ground.
39 A15m/A7/P2.7 bidirectional Port 2.7 I/O; external memory address bit 15 in multiplexed mode or bit 7 in non-multiplexed mode.
40 A14m/A6/P2.6 bidirectional Port 2.6 I/O; external memory address bit 14 in multiplexed mode or bit 6 in non-multiplexed mode.
41 A13m/A5/P2.5 bidirectional Port 2.5 I/O; external memory address bit 13 in multiplexed mode or bit 5 in non-multiplexed mode.
42 A12m/A4/P2.4 bidirectional Port 2.4 I/O; external memory address bit 12 in multiplexed mode or bit 4 in non-multiplexed mode.
43 A11m/A3/P2.3 bidirectional Port 2.3 I/O; external memory address bit 11 in multiplexed mode or bit 3 in non-multiplexed mode.
44 A10m/A2/P2.2 bidirectional Port 2.2 I/O; external memory address bit 10 in multiplexed mode or bit 2 in non-multiplexed mode.
45 A9m/A1/P2.1 bidirectional Port 2.1 I/O; external memory address bit 9 in multiplexed mode or bit 1 in non-multiplexed mode.
46 A8m/A0/P2.0 bidirectional Port 2.0 I/O; external memory address bit 8 in multiplexed mode or bit 0 in non-multiplexed mode.
47 AD7/D7/P3.7/IE7 bidirectional Port 3.7 I/O; external memory address/data bit 7 (multiplexed) or data bit 7 (non-multiplexed); can also generate edge-triggered external interrupt IE7.
48 AD6/D6/P3.6/IE6 bidirectional Port 3.6 I/O; external memory address/data bit 6 (multiplexed) or data bit 6 (non-multiplexed); can also generate edge-triggered external interrupt IE6.
49 AD5/D5/P3.5 bidirectional Port 3.5 I/O; external memory address/data bit 5 (multiplexed) or data bit 5 (non-multiplexed).
50 AD4/D4/P3.4 bidirectional Port 3.4 I/O; external memory address/data bit 4 (multiplexed) or data bit 4 (non-multiplexed).
51 AD3/D3/P3.3 bidirectional Port 3.3 I/O; external memory address/data bit 3 (multiplexed) or data bit 3 (non-multiplexed).
52 AD2/D2/P3.2 bidirectional Port 3.2 I/O; external memory address/data bit 2 (multiplexed) or data bit 2 (non-multiplexed).
53 AD1/D1/P3.1 bidirectional Port 3.1 I/O; external memory address/data bit 1 (multiplexed) or data bit 1 (non-multiplexed).
54 AD0/D0/P3.0 bidirectional Port 3.0 I/O; external memory address/data bit 0 (multiplexed) or data bit 0 (non-multiplexed).
55 /WR/P0.7 bidirectional /WR strobe for the external memory bus; otherwise Port 0.7 I/O, open-drain by default and push-pull when P0MDOUT.7 is 1.
56 /RD/P0.6 bidirectional /RD strobe for the external memory bus; otherwise Port 0.6 I/O, open-drain by default and push-pull when P0MDOUT.6 is 1.
57 ALE/P0.5 bidirectional ALE strobe for the external memory address bus in multiplexed mode; otherwise Port 0.5 I/O, open-drain by default and push-pull when P0MDOUT.5 is 1.
58 P0.4 bidirectional Port 0.4 I/O; open-drain by default, push-pull when P0MDOUT.4 is 1, and assignable to crossbar peripherals.
59 P0.3 bidirectional Port 0.3 I/O; open-drain by default, push-pull when P0MDOUT.3 is 1, and assignable to crossbar peripherals.
60 P0.2 bidirectional Port 0.2 I/O; open-drain by default, push-pull when P0MDOUT.2 is 1, and assignable to crossbar peripherals.
61 P0.1 bidirectional Port 0.1 I/O; open-drain by default, push-pull when P0MDOUT.1 is 1, and assignable to crossbar peripherals.
62 P0.0 bidirectional Port 0.0 I/O; open-drain by default, push-pull when P0MDOUT.0 is 1, and assignable to crossbar peripherals.
63 DGND power_in Digital Ground; must be tied to ground.
64 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
65 AD7/D7/P7.7 bidirectional Port 7.7 I/O; external memory address/data bit 7 (multiplexed) or data bit 7 (non-multiplexed).
66 AD6/D6/P7.6 bidirectional Port 7.6 I/O; external memory address/data bit 6 (multiplexed) or data bit 6 (non-multiplexed).
67 AD5/D5/P7.5 bidirectional Port 7.5 I/O; external memory address/data bit 5 (multiplexed) or data bit 5 (non-multiplexed).
68 AD4/D4/P7.4 bidirectional Port 7.4 I/O; external memory address/data bit 4 (multiplexed) or data bit 4 (non-multiplexed).
69 AD3/D3/P7.3 bidirectional Port 7.3 I/O; external memory address/data bit 3 (multiplexed) or data bit 3 (non-multiplexed).
70 AD2/D2/P7.2 bidirectional Port 7.2 I/O; external memory address/data bit 2 (multiplexed) or data bit 2 (non-multiplexed).
71 AD1/D1/P7.1 bidirectional Port 7.1 I/O; external memory address/data bit 1 (multiplexed) or data bit 1 (non-multiplexed).
72 AD0/D0/P7.0 bidirectional Port 7.0 I/O; external memory address/data bit 0 (multiplexed) or data bit 0 (non-multiplexed).
73 A15m/A7/P6.7 bidirectional Port 6.7 I/O; external memory address bit 15 in multiplexed mode or bit 7 in non-multiplexed mode.
74 A14m/A6/P6.6 bidirectional Port 6.6 I/O; external memory address bit 14 in multiplexed mode or bit 6 in non-multiplexed mode.
75 A13m/A5/P6.5 bidirectional Port 6.5 I/O; external memory address bit 13 in multiplexed mode or bit 5 in non-multiplexed mode.
76 A12m/A4/P6.4 bidirectional Port 6.4 I/O; external memory address bit 12 in multiplexed mode or bit 4 in non-multiplexed mode.
77 A11m/A3/P6.3 bidirectional Port 6.3 I/O; external memory address bit 11 in multiplexed mode or bit 3 in non-multiplexed mode.
78 A10m/A2/P6.2 bidirectional Port 6.2 I/O; external memory address bit 10 in multiplexed mode or bit 2 in non-multiplexed mode.
79 A9m/A1/P6.1 bidirectional Port 6.1 I/O; external memory address bit 9 in multiplexed mode or bit 1 in non-multiplexed mode.
80 A8m/A0/P6.0 bidirectional Port 6.0 I/O; external memory address bit 8 in multiplexed mode or bit 0 in non-multiplexed mode.
81 A15/P5.7 bidirectional Port 5.7 I/O; external memory address bit 15 in non-multiplexed mode.
82 A14/P5.6 bidirectional Port 5.6 I/O; external memory address bit 14 in non-multiplexed mode.
83 A13/P5.5 bidirectional Port 5.5 I/O; external memory address bit 13 in non-multiplexed mode.
84 A12/P5.4 bidirectional Port 5.4 I/O; external memory address bit 12 in non-multiplexed mode.
85 A11/P5.3 bidirectional Port 5.3 I/O; external memory address bit 11 in non-multiplexed mode.
86 A10/P5.2 bidirectional Port 5.2 I/O; external memory address bit 10 in non-multiplexed mode.
87 A9/P5.1 bidirectional Port 5.1 I/O; external memory address bit 9 in non-multiplexed mode.
88 A8/P5.0 bidirectional Port 5.0 I/O; external memory address bit 8 in non-multiplexed mode.
89 DGND power_in Digital Ground; must be tied to ground.
90 VDD power_in Digital Supply Voltage; must be tied to +2.7 to +3.6 V.
91 /WR/P4.7 bidirectional /WR strobe for the external memory bus; otherwise Port 4.7 I/O.
92 /RD/P4.6 bidirectional /RD strobe for the external memory bus; otherwise Port 4.6 I/O.
93 ALE/P4.5 bidirectional ALE strobe for the external memory address bus in multiplexed mode; otherwise Port 4.5 I/O.
94 P4.4 bidirectional Port 4.4 general-purpose I/O.
95 P4.3 bidirectional Port 4.3 general-purpose I/O.
96 P4.2 bidirectional Port 4.2 general-purpose I/O.
97 P4.1 bidirectional Port 4.1 general-purpose I/O.
98 P4.0 bidirectional Port 4.0 general-purpose I/O.
99 DAC1 output Digital to Analog Converter 1 voltage output (see DAC specification).
100 DAC0 output Digital to Analog Converter 0 voltage output (see DAC specification).

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 31
Storage Temperature -65 150 °C 31
Voltage on any Pin (except VDD and Port I/O) with respect to DGND -0.3 V with respect to DGND 31
Voltage on any Port I/O Pin or /RST with respect to DGND -0.3 5.8 V with respect to DGND 31
Voltage on VDD with respect to DGND -0.3 4.2 V with respect to DGND 31
Maximum Total current through VDD, AV+, DGND, and AGND 800 mA 31
Maximum output current sunk by any Port pin 100 mA 31
Maximum output current sunk by any other I/O pin 50 mA 31
Maximum output current sourced by any Port pin 100 mA 31
Maximum output current sourced by any other I/O pin 50 mA 31
Analog Supply Voltage AV+ 2.7 3 3.6 V 32
Analog Supply Current 1.7 mA AV+=2.7 V, Internal REF, ADC, DAC, Comparators all active 32
Analog Supply Current with analog sub-systems inactive 0.2 µA AV+=2.7 V, Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled, VDD Monitor disabled 32
Analog-to-Digital Supply Delta (/VDD - AV+/) 0.5 V 32
Digital Supply Voltage VDD 2.7 3 3.6 V 32
Digital Supply Current with CPU active 10 mA VDD=2.7 V, Clock=25 MHz 32
Digital Supply Current with CPU active 0.5 mA VDD=2.7 V, Clock=1 MHz 32
Digital Supply Current with CPU active 20 µA VDD=2.7 V, Clock=32 kHz 32
Digital Supply Current (shutdown) 0.2 µA VDD=2.7 V, Oscillator not running, VDD Monitor disabled 32
Digital Supply RAM Data Retention Voltage 1.5 V 32
Specified Operating Temperature Range -40 85 °C 32
SYSCLK (system clock frequency) SYSCLK 0 25 MHz 32
SYSCLK low time Tsysl 18 ns 32
SYSCLK high time Tsysh 18 ns 32
Integral Nonlinearity -1 1 LSB 74
Differential Nonlinearity -1 1 LSB Guaranteed Monotonic 74
Offset Error -0.5 0.5 LSB 74
Signal-to-Noise Plus Distortion 59 dB 74
Total Harmonic Distortion -70 dB Up to the 5th harmonic 74
Spurious-Free Dynamic Range 80 dB 74
SAR Clock Frequency 2.5 MHz 74
Track/Hold Acquisition Time 1.5 µs 74
Power Supply Current (AV+ supplied to ADC) 450 900 µA Operating Mode, 100 ksps 74
Power Supply Rejection -0.3 0.3 mV/V 74
Integral Nonlinearity -1 1 LSB 82
Signal-to-Noise Plus Distortion 45 47 dB 82
Power Supply Current (AV+ supplied to ADC1) 420 900 µA Operating Mode, 500 ksps 82
Power Supply Rejection -0.3 0.3 mV/V 82
Integral Nonlinearity -2 2 LSB 89
Differential Nonlinearity -1 1 LSB 89
Offset Error -30 3 30 mV Data Word = 0x014 89
Output Short-Circuit Current 15 mA Data Word = 0xFFF 89
Power Supply Current (AV+ supplied to DAC) 110 400 µA Data Word = 0x7FF 89
Output Voltage 2.36 2.43 2.48 V 25°C ambient 92
VREF Short-Circuit Current 30 mA 92
External Reference Input Voltage Range 1 V 92
VREF Temperature Coefficient 15 ppm/°C 92
Response Time 1 4 µs CP+ - CP- = 100 mV 99
Input Offset Voltage -10 10 mV 99
Input Bias Current -5 0.001 5 nA 99
Supply Current (each comparator) 1.5 10 µA Operating Mode (each comparator) at DC 99
/RST Output Low Voltage 0.6 V IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 133
VDD POR Threshold VRST 2.4 2.55 2.7 V 133
Reset Time Delay 80 100 120 ms /RST rising edge after VDD crosses VRST threshold 133
Internal Oscillator Frequency 1.5 2 2.4 MHz OSCICN.[1:0] = 00 136
Internal Oscillator Frequency 3.1 4 4.8 MHz OSCICN.[1:0] = 01 136
Internal Oscillator Frequency 6.2 8 9.6 MHz OSCICN.[1:0] = 10 136
Internal Oscillator Frequency 12.3 16 19.2 MHz OSCICN.[1:0] = 11 136

CAD (KiCad official)

  • Symbol: C8051F022-GQR
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: c8051f022-gqr-etched.step / c8051f022-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f022-gqr.step / c8051f022-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (272 pp, sha256 5313ddbcc59a6246, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF