component
C8051F005-GQ
Public Made by Adomby adom
SKYWORKS/SILICON LABS Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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C8051F005-GQ
SKYWORKS/SILICON LABS · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
C8051F005-GQ from SKYWORKS/SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1- | input | Comparator 1 inverting input. |
| 2 | CP1+ | input | Comparator 1 non-inverting input. |
| 3 | CP0- | input | Comparator 0 inverting input. |
| 4 | CP0+ | input | Comparator 0 non-inverting input. |
| 5 | AGND | power_in | Analog ground. |
| 6 | VREF | power_in | Voltage reference; as an input it is the MCU voltage reference, otherwise the internal reference drives this pin. |
| 7 | AIN0 | input | Analog mux channel input 0. |
| 8 | AIN1 | input | Analog mux channel input 1. |
| 9 | AIN2 | input | Analog mux channel input 2. |
| 10 | AIN3 | input | Analog mux channel input 3. |
| 11 | AIN4 | input | Analog mux channel input 4. |
| 12 | AIN5 | input | Analog mux channel input 5. |
| 13 | AIN6 | input | Analog mux channel input 6. |
| 14 | AIN7 | input | Analog mux channel input 7. |
| 15 | AGND | power_in | Analog ground. |
| 16 | AV+ | power_in | Positive analog voltage supply, 2.7 V to 3.6 V. |
| 17 | AV+ | power_in | Positive analog voltage supply, 2.7 V to 3.6 V. |
| 18 | XTAL1 | input | Crystal input; return for the internal oscillator circuit, becomes the system clock if overdriven by an external CMOS clock. |
| 19 | XTAL2 | output | Crystal output; excitation driver for a crystal or ceramic resonator. |
| 20 | /RST | bidirectional | Chip reset; open-drain output of the VDD monitor driven low when VDD is below 2.7 V, and an external source can force reset by driving it low. |
| 21 | TMS | input | JTAG test-mode select with internal pull-up. |
| 22 | TCK | input | JTAG test clock with internal pull-up. |
| 23 | P3.3 | bidirectional | Port 3 bit 3 digital I/O. |
| 24 | P3.2 | bidirectional | Port 3 bit 2 digital I/O. |
| 25 | P3.1 | bidirectional | Port 3 bit 1 digital I/O. |
| 26 | P3.0 | bidirectional | Port 3 bit 0 digital I/O. |
| 27 | P2.1 | bidirectional | Port 2 bit 1 digital I/O. |
| 28 | TDI | input | JTAG test data input with internal pull-up, latched on a rising edge of TCK. |
| 29 | TDO | tri_state | JTAG test data output with internal pull-up, shifted out on the falling edge of TCK; tri-state driver. |
| 30 | DGND | power_in | Digital ground. |
| 31 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 32 | P1.5 | bidirectional | Port 1 bit 5 digital I/O. |
| 33 | P2.0 | bidirectional | Port 2 bit 0 digital I/O. |
| 34 | P1.4 | bidirectional | Port 1 bit 4 digital I/O. |
| 35 | P1.3 | bidirectional | Port 1 bit 3 digital I/O. |
| 36 | P1.2 | bidirectional | Port 1 bit 2 digital I/O. |
| 37 | P1.1 | bidirectional | Port 1 bit 1 digital I/O. |
| 38 | P1.0 | bidirectional | Port 1 bit 0 digital I/O. |
| 39 | P0.0 | bidirectional | Port 0 bit 0 digital I/O. |
| 40 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 41 | DGND | power_in | Digital ground. |
| 42 | P0.1 | bidirectional | Port 0 bit 1 digital I/O. |
| 43 | P2.7 | bidirectional | Port 2 bit 7 digital I/O. |
| 44 | P2.6 | bidirectional | Port 2 bit 6 digital I/O. |
| 45 | P3.7 | bidirectional | Port 3 bit 7 digital I/O. |
| 46 | P3.6 | bidirectional | Port 3 bit 6 digital I/O. |
| 47 | P0.2 | bidirectional | Port 0 bit 2 digital I/O. |
| 48 | P0.3 | bidirectional | Port 0 bit 3 digital I/O. |
| 49 | P0.4 | bidirectional | Port 0 bit 4 digital I/O. |
| 50 | P0.5 | bidirectional | Port 0 bit 5 digital I/O. |
| 51 | P2.5 | bidirectional | Port 2 bit 5 digital I/O. |
| 52 | P2.4 | bidirectional | Port 2 bit 4 digital I/O. |
| 53 | P2.3 | bidirectional | Port 2 bit 3 digital I/O. |
| 54 | P2.2 | bidirectional | Port 2 bit 2 digital I/O. |
| 55 | P0.6 | bidirectional | Port 0 bit 6 digital I/O. |
| 56 | P0.7 | bidirectional | Port 0 bit 7 digital I/O. |
| 57 | P3.5 | bidirectional | Port 3 bit 5 digital I/O. |
| 58 | P3.4 | bidirectional | Port 3 bit 4 digital I/O. |
| 59 | P1.7 | bidirectional | Port 1 bit 7 digital I/O. |
| 60 | P1.6 | bidirectional | Port 1 bit 6 digital I/O. |
| 61 | DGND | power_in | Digital ground. |
| 62 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 63 | DAC1 | output | Digital-to-analog converter 1 voltage output. |
| 64 | DAC0 | output | Digital-to-analog converter 0 voltage output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS/SILICON LABS |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage | AV+ | 2.7 | 3 | 3.6 | V | -40°C to +85°C | 20 |
| Analog Supply Current | 1 | 2 | mA | Internal REF, ADC, DAC, Comparators all active | 20 | ||
| Analog Supply Current with analog sub-systems inactive | 5 | 20 | µA | Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled | 20 | ||
| Analog-to-Digital Supply Delta | /VDD, AV+/ | 0.5 | V | 20 | |||
| Digital Supply Voltage | VDD | 2.7 | 3 | 3.6 | V | 20 | |
| Digital Supply Current with CPU active | 12.5 | mA | VDD = 2.7V, Clock=25MHz | 20 | |||
| Digital Supply Current with CPU active | 0.5 | mA | VDD = 2.7V, Clock=1MHz | 20 | |||
| Digital Supply Current with CPU active | 10 | µA | VDD = 2.7V, Clock=32kHz | 20 | |||
| Digital Supply Current (shutdown) | 5 | µA | Oscillator not running | 20 | |||
| Digital Supply RAM Data Retention Voltage | 1.5 | V | 20 | ||||
| Specified Operating Temperature Range | -40 | 85 | °C | 20 | |||
| System Clock Frequency | SYSCLK | 0 | 25 | MHz | C8051F005/6/7, C8051F015/6/7 (Note 2) | 20 | |
| SYSCLK Low Time | Tsysl | 18 | ns | 20 | |||
| SYSCLK High Time | Tsysh | 18 | ns | 20 | |||
| Ambient temperature under bias | -55 | 125 | °C | 20 | |||
| Storage Temperature | -65 | 150 | °C | 20 | |||
| Voltage on any Port I/O Pin or /RST with respect to DGND | -0.3 | 5.8 | V | 20 | |||
| Voltage on VDD with respect to DGND | VDD | -0.3 | 4.2 | V | 20 | ||
| Maximum output current sunk by any other I/O pin | 25 | mA | 20 | ||||
| Maximum output current sourced by any other I/O pin | 25 | mA | 20 | ||||
| ADC Resolution | 12 | bits | VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V, PGA Gain = 1 | 39 | |||
| ADC Integral Nonlinearity | INL | 1 | LSB | printed ± 1 | 39 | ||
| ADC Differential Nonlinearity | DNL | -1 | 1 | LSB | Guaranteed Monotonic | 39 | |
| ADC Offset Error | -3 | 1 | LSB | printed -3 ± 1 | 39 | ||
| ADC Full Scale Error | -7 | 3 | LSB | Differential mode, printed -7 ± 3 | 39 | ||
| ADC Offset Temperature Coefficient | 0.25 | ppm/°C | printed ± 0.25 | 39 | |||
| Signal-to-Noise Plus Distortion | SNR+D | 66 | 69 | dB | 10kHz sine-wave input, 0 to -1dB of full scale, 100ksps | 39 | |
| Total Harmonic Distortion | THD | -75 | dB | Up to the 5th harmonic | 39 | ||
| Spurious-Free Dynamic Range | SFDR | 80 | dB | 39 | |||
| SAR Clock Frequency | 2.5 | MHz | C8051F005, ‘F006, ‘F007 | 39 | |||
| Track/Hold Acquisition Time | 1.5 | µs | 39 | ||||
| Throughput Rate | 100 | ksps | 39 | ||||
| ADC Input Capacitance | 10 | pF | 39 | ||||
| Temperature Sensor Absolute Accuracy | -3 | 3 | °C | 39 | |||
| ADC Power Supply Current | 450 | 900 | µA | Operating Mode, 100ksps | 39 | ||
| DAC Resolution | 12 | bits | VDD = 3.0V, AV+ = 3.0V, REF = 2.40V | 54 | |||
| DAC Integral Nonlinearity | INL | -2 | 2 | LSB | For Data Word Range 0x014 to 0xFEB | 54 | |
| DAC Differential Nonlinearity | DNL | -1 | 1 | LSB | Guaranteed Monotonic (codes 0x014 to 0xFEB) | 54 | |
| DAC Offset Error | -30 | 3 | 30 | mV | Data Word = 0x014 | 54 | |
| DAC Full-Scale Error | -60 | 20 | 60 | mV | 54 | ||
| DAC Output Current | 300 | µA | printed ±300 | 54 | |||
| DAC Power Supply Current | 110 | 400 | µA | Data Word = 0x7FF, each DAC | 54 | ||
| Comparator Response Time1 | 4 | µs | (CP+), (CP-) = 100mV (Note 1) | 59 | |||
| Comparator Positive Hysteresis2 | 2 | 4.5 | 7 | mV | CPnHYP1-0 = 01 | 59 | |
| Comparator Positive Hysteresis3 | 4 | 9 | 13 | mV | CPnHYP1-0 = 10 | 59 | |
| Comparator Positive Hysteresis4 | 10 | 17 | 25 | mV | CPnHYP1-0 = 11 | 59 | |
| Comparator Input Bias Current | -5 | 0.001 | 5 | nA | 59 | ||
| Comparator Input Offset Voltage | -10 | 10 | mV | 59 | |||
| Comparator Supply Current | 1.5 | 10 | µA | Operating Mode (each comparator) at DC | 59 | ||
| Reference Output Voltage | VREF | 2.34 | 2.43 | 2.5 | V | 25°C ambient, REFBE = 1 | 61 |
| VREF Short Circuit Current | 30 | mA | 61 | ||||
| VREF Power Supply Current | 50 | µA | supplied by AV+ | 61 | |||
| VREF Temperature Coefficient | 15 | ppm/°C | 61 | ||||
| External Reference Input Voltage Range | 1 | V | REFBE = 0, max (AV+), 0.3V | 61 |
CAD (KiCad official)
- Symbol:
C8051F005-GQ - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
c8051f005-gq-etched.step/c8051f005-gq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);c8051f005-gq.step/c8051f005-gq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS/SILICON LABS datasheet (170 pp, sha256
cd2d316bae6ccccd, retrieved 2026-11-02, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# C8051F005-GQ
**SKYWORKS/SILICON LABS** · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
C8051F005-GQ from SKYWORKS/SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1- | input | Comparator 1 inverting input. |
| 2 | CP1+ | input | Comparator 1 non-inverting input. |
| 3 | CP0- | input | Comparator 0 inverting input. |
| 4 | CP0+ | input | Comparator 0 non-inverting input. |
| 5 | AGND | power_in | Analog ground. |
| 6 | VREF | power_in | Voltage reference; as an input it is the MCU voltage reference, otherwise the internal reference drives this pin. |
| 7 | AIN0 | input | Analog mux channel input 0. |
| 8 | AIN1 | input | Analog mux channel input 1. |
| 9 | AIN2 | input | Analog mux channel input 2. |
| 10 | AIN3 | input | Analog mux channel input 3. |
| 11 | AIN4 | input | Analog mux channel input 4. |
| 12 | AIN5 | input | Analog mux channel input 5. |
| 13 | AIN6 | input | Analog mux channel input 6. |
| 14 | AIN7 | input | Analog mux channel input 7. |
| 15 | AGND | power_in | Analog ground. |
| 16 | AV+ | power_in | Positive analog voltage supply, 2.7 V to 3.6 V. |
| 17 | AV+ | power_in | Positive analog voltage supply, 2.7 V to 3.6 V. |
| 18 | XTAL1 | input | Crystal input; return for the internal oscillator circuit, becomes the system clock if overdriven by an external CMOS clock. |
| 19 | XTAL2 | output | Crystal output; excitation driver for a crystal or ceramic resonator. |
| 20 | /RST | bidirectional | Chip reset; open-drain output of the VDD monitor driven low when VDD is below 2.7 V, and an external source can force reset by driving it low. |
| 21 | TMS | input | JTAG test-mode select with internal pull-up. |
| 22 | TCK | input | JTAG test clock with internal pull-up. |
| 23 | P3.3 | bidirectional | Port 3 bit 3 digital I/O. |
| 24 | P3.2 | bidirectional | Port 3 bit 2 digital I/O. |
| 25 | P3.1 | bidirectional | Port 3 bit 1 digital I/O. |
| 26 | P3.0 | bidirectional | Port 3 bit 0 digital I/O. |
| 27 | P2.1 | bidirectional | Port 2 bit 1 digital I/O. |
| 28 | TDI | input | JTAG test data input with internal pull-up, latched on a rising edge of TCK. |
| 29 | TDO | tri_state | JTAG test data output with internal pull-up, shifted out on the falling edge of TCK; tri-state driver. |
| 30 | DGND | power_in | Digital ground. |
| 31 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 32 | P1.5 | bidirectional | Port 1 bit 5 digital I/O. |
| 33 | P2.0 | bidirectional | Port 2 bit 0 digital I/O. |
| 34 | P1.4 | bidirectional | Port 1 bit 4 digital I/O. |
| 35 | P1.3 | bidirectional | Port 1 bit 3 digital I/O. |
| 36 | P1.2 | bidirectional | Port 1 bit 2 digital I/O. |
| 37 | P1.1 | bidirectional | Port 1 bit 1 digital I/O. |
| 38 | P1.0 | bidirectional | Port 1 bit 0 digital I/O. |
| 39 | P0.0 | bidirectional | Port 0 bit 0 digital I/O. |
| 40 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 41 | DGND | power_in | Digital ground. |
| 42 | P0.1 | bidirectional | Port 0 bit 1 digital I/O. |
| 43 | P2.7 | bidirectional | Port 2 bit 7 digital I/O. |
| 44 | P2.6 | bidirectional | Port 2 bit 6 digital I/O. |
| 45 | P3.7 | bidirectional | Port 3 bit 7 digital I/O. |
| 46 | P3.6 | bidirectional | Port 3 bit 6 digital I/O. |
| 47 | P0.2 | bidirectional | Port 0 bit 2 digital I/O. |
| 48 | P0.3 | bidirectional | Port 0 bit 3 digital I/O. |
| 49 | P0.4 | bidirectional | Port 0 bit 4 digital I/O. |
| 50 | P0.5 | bidirectional | Port 0 bit 5 digital I/O. |
| 51 | P2.5 | bidirectional | Port 2 bit 5 digital I/O. |
| 52 | P2.4 | bidirectional | Port 2 bit 4 digital I/O. |
| 53 | P2.3 | bidirectional | Port 2 bit 3 digital I/O. |
| 54 | P2.2 | bidirectional | Port 2 bit 2 digital I/O. |
| 55 | P0.6 | bidirectional | Port 0 bit 6 digital I/O. |
| 56 | P0.7 | bidirectional | Port 0 bit 7 digital I/O. |
| 57 | P3.5 | bidirectional | Port 3 bit 5 digital I/O. |
| 58 | P3.4 | bidirectional | Port 3 bit 4 digital I/O. |
| 59 | P1.7 | bidirectional | Port 1 bit 7 digital I/O. |
| 60 | P1.6 | bidirectional | Port 1 bit 6 digital I/O. |
| 61 | DGND | power_in | Digital ground. |
| 62 | VDD | power_in | Digital voltage supply, 2.7 V to 3.6 V. |
| 63 | DAC1 | output | Digital-to-analog converter 1 voltage output. |
| 64 | DAC0 | output | Digital-to-analog converter 0 voltage output. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS/SILICON LABS |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage | AV+ | 2.7 | 3 | 3.6 | V | -40°C to +85°C | 20 |
| Analog Supply Current | | | 1 | 2 | mA | Internal REF, ADC, DAC, Comparators all active | 20 |
| Analog Supply Current with analog sub-systems inactive | | | 5 | 20 | µA | Internal REF, ADC, DAC, Comparators all disabled, oscillator disabled | 20 |
| Analog-to-Digital Supply Delta | /VDD, AV+/ | | | 0.5 | V | | 20 |
| Digital Supply Voltage | VDD | 2.7 | 3 | 3.6 | V | | 20 |
| Digital Supply Current with CPU active | | | 12.5 | | mA | VDD = 2.7V, Clock=25MHz | 20 |
| Digital Supply Current with CPU active | | | 0.5 | | mA | VDD = 2.7V, Clock=1MHz | 20 |
| Digital Supply Current with CPU active | | | 10 | | µA | VDD = 2.7V, Clock=32kHz | 20 |
| Digital Supply Current (shutdown) | | | 5 | | µA | Oscillator not running | 20 |
| Digital Supply RAM Data Retention Voltage | | | 1.5 | | V | | 20 |
| Specified Operating Temperature Range | | -40 | | 85 | °C | | 20 |
| System Clock Frequency | SYSCLK | 0 | | 25 | MHz | C8051F005/6/7, C8051F015/6/7 (Note 2) | 20 |
| SYSCLK Low Time | Tsysl | 18 | | | ns | | 20 |
| SYSCLK High Time | Tsysh | 18 | | | ns | | 20 |
| Ambient temperature under bias | | -55 | | 125 | °C | | 20 |
| Storage Temperature | | -65 | | 150 | °C | | 20 |
| Voltage on any Port I/O Pin or /RST with respect to DGND | | -0.3 | | 5.8 | V | | 20 |
| Voltage on VDD with respect to DGND | VDD | -0.3 | | 4.2 | V | | 20 |
| Maximum output current sunk by any other I/O pin | | | | 25 | mA | | 20 |
| Maximum output current sourced by any other I/O pin | | | | 25 | mA | | 20 |
| ADC Resolution | | | 12 | | bits | VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V, PGA Gain = 1 | 39 |
| ADC Integral Nonlinearity | INL | | | 1 | LSB | printed ± 1 | 39 |
| ADC Differential Nonlinearity | DNL | -1 | | 1 | LSB | Guaranteed Monotonic | 39 |
| ADC Offset Error | | -3 | 1 | | LSB | printed -3 ± 1 | 39 |
| ADC Full Scale Error | | -7 | 3 | | LSB | Differential mode, printed -7 ± 3 | 39 |
| ADC Offset Temperature Coefficient | | | 0.25 | | ppm/°C | printed ± 0.25 | 39 |
| Signal-to-Noise Plus Distortion | SNR+D | 66 | 69 | | dB | 10kHz sine-wave input, 0 to -1dB of full scale, 100ksps | 39 |
| Total Harmonic Distortion | THD | | -75 | | dB | Up to the 5th harmonic | 39 |
| Spurious-Free Dynamic Range | SFDR | | 80 | | dB | | 39 |
| SAR Clock Frequency | | | | 2.5 | MHz | C8051F005, ‘F006, ‘F007 | 39 |
| Track/Hold Acquisition Time | | 1.5 | | | µs | | 39 |
| Throughput Rate | | | | 100 | ksps | | 39 |
| ADC Input Capacitance | | | 10 | | pF | | 39 |
| Temperature Sensor Absolute Accuracy | | -3 | | 3 | °C | | 39 |
| ADC Power Supply Current | | | 450 | 900 | µA | Operating Mode, 100ksps | 39 |
| DAC Resolution | | | 12 | | bits | VDD = 3.0V, AV+ = 3.0V, REF = 2.40V | 54 |
| DAC Integral Nonlinearity | INL | -2 | | 2 | LSB | For Data Word Range 0x014 to 0xFEB | 54 |
| DAC Differential Nonlinearity | DNL | -1 | | 1 | LSB | Guaranteed Monotonic (codes 0x014 to 0xFEB) | 54 |
| DAC Offset Error | | -30 | 3 | 30 | mV | Data Word = 0x014 | 54 |
| DAC Full-Scale Error | | -60 | 20 | 60 | mV | | 54 |
| DAC Output Current | | | 300 | | µA | printed ±300 | 54 |
| DAC Power Supply Current | | | 110 | 400 | µA | Data Word = 0x7FF, each DAC | 54 |
| Comparator Response Time1 | | | 4 | | µs | (CP+), (CP-) = 100mV (Note 1) | 59 |
| Comparator Positive Hysteresis2 | | 2 | 4.5 | 7 | mV | CPnHYP1-0 = 01 | 59 |
| Comparator Positive Hysteresis3 | | 4 | 9 | 13 | mV | CPnHYP1-0 = 10 | 59 |
| Comparator Positive Hysteresis4 | | 10 | 17 | 25 | mV | CPnHYP1-0 = 11 | 59 |
| Comparator Input Bias Current | | -5 | 0.001 | 5 | nA | | 59 |
| Comparator Input Offset Voltage | | -10 | | 10 | mV | | 59 |
| Comparator Supply Current | | | 1.5 | 10 | µA | Operating Mode (each comparator) at DC | 59 |
| Reference Output Voltage | VREF | 2.34 | 2.43 | 2.5 | V | 25°C ambient, REFBE = 1 | 61 |
| VREF Short Circuit Current | | | | 30 | mA | | 61 |
| VREF Power Supply Current | | | | 50 | µA | supplied by AV+ | 61 |
| VREF Temperature Coefficient | | | 15 | | ppm/°C | | 61 |
| External Reference Input Voltage Range | | 1 | | | V | REFBE = 0, max (AV+), 0.3V | 61 |
## CAD (KiCad official)
- Symbol: `C8051F005-GQ`
- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`
- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `c8051f005-gq-etched.step` / `c8051f005-gq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `c8051f005-gq.step` / `c8051f005-gq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SKYWORKS/SILICON LABS datasheet](docs/c8051f005-gq-datasheet.pdf) (170 pp, sha256 `cd2d316bae6ccccd`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/c8051f005-gq-datasheet.pdf)