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BY25Q64ASSIG

Public Made by Adom

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BOYAMICRO NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BY25Q64ASSIG

BOYAMICRO · NOR FLASH · SOP-8-208mil

BY25Q64ASSIG from BOYAMICRO, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /CS input Chip select, active low: when high the device is deselected, ignores inputs and its outputs are high-impedance, and a falling edge on /CS is required after power-up before any instruction.
2 SO (IO1) bidirectional Serial data output for single-bit instructions and IO1 for Dual/Quad instructions; data is shifted out on the falling edge of SCLK.
3 /WP (IO2) bidirectional Write protect: when driven low with SRP1/SRP0 set as specified, Status Register writes are blocked; it has an internal pull-up, may be left unconnected if unused, and becomes IO2 in Quad mode (not available when QE=1).
4 VSS power_in Ground reference for the device.
5 SI (IO0) bidirectional Serial data input for single-bit instructions and IO0 for Dual/Quad instructions; values are latched on the rising edge of SCLK.
6 SCLK input Serial clock providing the synchronization reference for the SPI interface; instructions, addresses and data are latched on its rising edge and output changes after its falling edge.
7 /HOLD (IO3) bidirectional Pauses serial communication when driven low (only when QE=0, otherwise a dedicated I/O); it has an internal pull-up, may be left unconnected if unused, and becomes IO3 in Quad mode.
8 VCC power_in Core and I/O power supply, which must be held stable within VCC(min) to VCC(max) (2.7 V to 3.6 V per the Features list) during all operations.

Key specifications

Parameter Value
Manufacturer BOYAMICRO
Package SOP-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 4 V 58
Voltage Applied to Any Pin VIO -0.5 4 V Relative to Ground 58
Transient Voltage on any Pin VIOT -2 V <20nS Transient, Relative to Ground; upper limit printed as VCC+2.0V 58
Storage Temperature TSTG -65 150 °C 58
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model (JEDEC JESD22-A114) 58
Supply Voltage VCC 2.7 3.6 V 58
Operating Temperature, Commercial TA 0 70 °C Commercial 58
Operating Temperature, Industrial TA -40 85 °C Industrial 58
Minimum Pattern Data Retention Time 10 Years 150°C 58
Minimum Pattern Data Retention Time 20 Years 125°C 58
Erase/Program Endurance 100 K Cycles -40 to 85°C 58
Input Voltage Respect To VSS On I/O Pins -1 V Latch-up; upper limit printed as VCC+1.0V 59
VCC Current (latch-up) -100 100 mA 59
VCC(min) To /CS Low tVSL 300 us 59
Input Leakage Current ILI -2 2 µA 60
Standby Current ICC1 13 25 µA /CS=VCC, VIN=VCC or VSS 60
Deep Power-Down Current ICC2 2 5 µA /CS=VCC, VIN=VCC or VSS 60
Operating Current (Read) ICC3 15 20 mA SCLK=0.1VCC/0.9VCC, at 120MHz, Q=Open(1,,2*4 I/O) 60
Operating Current (Page Program) ICC4 15 mA /CS=VCC 60
Operating Current (WRSR) ICC5 5 mA /CS=VCC 60
Operating Current (Sector Erase) ICC6 20 mA /CS=VCC 60
Operating Current (Block Erase) ICC7 20 mA /CS=VCC 60
Operating Current (Chip Erase) ICC8 20 mA /CS=VCC 60
Input Low Voltage VIL -0.5 V 60
Output Low Voltage VOL 0.4 V IOL =100µA 60
Clock frequency for all instructions, except Read Data(03H) Fc 108 MHz 61
Clock freq. for Read Data instruction (03H) fR 55 MHz 61
Serial Clock High Time tCLH 4 ns 61
Serial Clock Low Time tCLL 4 ns 61
Serial Clock Rise Time (Slew Rate) tCLCH 0.1 V/ns see note 1: tested with clock frequency lower than 50 MHz 61
/CS Active Setup Time tSLCH 5 ns 61
/CS Active Hold Time tCHSH 5 ns 61
/CS Not Active Setup Time tSHCH 5 ns 61
/CS Not Active Hold Time tCHSL 5 ns 61
/CS High Time (read/write) tSHSL 20 ns 61
Output Disable Time tSHQZ 6 ns 61
Output Hold Time tCLQX 0 ns 61
Data In Setup Time tDVCH 2 ns 61
Data In Hold Time tCHDX 2 ns 61
/Hold Low Setup Time (relative to Clock) tHLCH 5 ns 61
/Hold High Setup Time (relative to Clock) tHHCH 5 ns 61
/Hold High Hold Time (relative to Clock) tCHHL 5 ns 61
/Hold Low Hold Time (relative to Clock) tCHHH 5 ns 61
/Hold Low To High-Z Output tHLQZ 6 ns 61
/Hold Low To Low-Z Output tHHQX 6 ns 61
Clock Low To Output Valid tCLQV 7 ns 62
Write Protect Setup Time Before /CS Low tWHSL 20 ns 62
Write Protect Hold Time After /CS High tSHWL 100 ns 62
/CS High To Deep Power-Down Mode tDP 20 µs 62
/CS High To Standby Mode Without Electronic Signature Read tRES1 20 µs 62
/CS High To Next Instruction After Suspend tSUS 20 µs 62
/CS High To Next Instruction After Reset(from read) tRST_R 20 62
Write Status Register Cycle Time tW 5 30 ms 62
Byte Program Time (First Byte) tBP1 30 50 µs 62
Additional Byte Program Time (After First Byte) tBP2 2.5 12 µs 62
Page Programming Time tPP 0.6 2.4 ms 62
Sector Erase Time tSE 50 300 ms 62
Block Erase Time (32K Bytes) tBE 0.15 1.6 S 32K Bytes 62
Block Erase Time (64K Bytes) tBE 0.25 2 S 64K Bytes 62
Chip Erase Time tCE 25 60 S 62

CAD (KiCad official)

  • Symbol: BY25Q64ASSIG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-208mil (KiCad packages3D, STEP)
  • 3D model files: by25q64assig-etched.step / by25q64assig-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); by25q64assig.step / by25q64assig.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BOYAMICRO datasheet (70 pp, sha256 a72d186387642daa, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF