component

BULN2803LVS

Public Made by Adom

by adom

BORN Darlington Transistor Arrays, SOIC-18-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistorsbuln2803lvsfactory-2.0.0extractor-text

Verified BULN2803LVS

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier lcsc, 18 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: BULN2803LVS · SOIC-18-300mil · 18 pins
  • ✓copper: 18 copper pads, none touching another net
  • ✓datasheet: all 18 pin names found in the 7-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-18W_7.5x11.6mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-27t93k_y/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.7)
  • ✓pads: 18 pins = 18 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 18 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 35 kB, viewers/symbol.html 15 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ buln2803lvs.kicad_sym✓ buln2803lvs.kicad_mod✓ buln2803lvs.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 9h ago
viewers buln2803lvs: viewers rendered from the public page · Ray 9h ago
buln2803lvs-etched.glb Publish 0.1.0 · Ray 9h ago
buln2803lvs-etched.step buln2803lvs: factory component page (tier=lcsc) · Ray 9h ago
buln2803lvs-hero.glb buln2803lvs: hero GLB from the etched model (keeps the MPN mark) · Ray 9h ago
buln2803lvs-hero.overlay.json buln2803lvs: hero GLB from the etched model (keeps the MPN mark) · Ray 9h ago
buln2803lvs.glb Publish 0.1.0 · Ray 9h ago
buln2803lvs.kicad_mod Publish 0.1.0 · Ray 9h ago
buln2803lvs.kicad_sym Publish 0.1.0 · Ray 9h ago
buln2803lvs.lbr Publish 0.1.0 · Ray 9h ago
buln2803lvs.step Publish 0.1.0 · Ray 9h ago
package.json Publish 0.1.0 · Ray 9h ago
page.json Set visibility: public · Ray 9h ago
README.md Publish 0.1.0 · Ray 9h ago
verification.json Verified: Published by the parts factory: tier lcsc, 18 pins · Ray 9h ago

BULN2803LVS

BORN · Darlington Transistor Arrays · SOIC-18-300mil

BULN2803LVS from BORN, in a SOIC-18-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Channel 1 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
2 2B input Channel 2 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
3 3B input Channel 3 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
4 4B input Channel 4 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
5 5B input Channel 5 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
6 6B input Channel 6 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
7 7B input Channel 7 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
8 8B input Channel 8 Darlington base input, which the datasheet states supports 1.8 V low-voltage input and TTL/CMOS logic signals.
9 GND power_in Common emitter shared by all channels, typically tied to ground.
10 COM bidirectional Common cathode node for the flyback clamp diodes, which the datasheet states is required for inductive loads.
11 8C output Channel 8 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
12 7C output Channel 7 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
13 6C output Channel 6 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
14 5C output Channel 5 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
15 4C output Channel 4 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
16 3C output Channel 3 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
17 2C output Channel 2 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.
18 1C output Channel 1 Darlington collector output, rated at 500 mA per pair with a 20 V collector-to-emitter maximum.

Key specifications

Parameter Value
Manufacturer BORN
Package SOIC-18-300mil
Category Transistors
Pins 18

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Collector-emitter voltage VCE 20 V At 25°C free-air temperature unless otherwise noted 3
Input voltage VI 20 V At 25°C free-air temperature unless otherwise noted; with respect to emitter/substrate terminal E 3
Peak collector current ICP 500 mA At 25°C free-air temperature unless otherwise noted 3
Output clamp current IOK 500 mA At 25°C free-air temperature unless otherwise noted 3
Total substrate-terminal current ITE -2 A At 25°C free-air temperature unless otherwise noted 3
Operating virtual junction temperature TJ -65 150 °C At 25°C free-air temperature unless otherwise noted 3
Storage temperature range TSTG -65 150 °C 3
Human body model ESD rating V(ESD) -2000 2000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 3
Charged device model ESD rating V(ESD) -500 500 V Charged device model (CDM), per JEDEC specification JESD22-C101 3
Collector-emitter voltage V(CE) 0 18 V Over operating free-air temperature range 3
Ambient temperature T(A) -40 85 °C Over operating free-air temperature range 3
Junction-to-ambient thermal resistance RθJA 66.4 °C/W SOIC 18 pins 3
Junction-to-case (top) thermal resistance RθJC(top) 29.5 °C/W SOIC 18 pins 3
Junction-to-board thermal resistance RθJB 33 °C/W SOIC 18 pins 3
Junction-to-top characterization parameter ψJT 6 °C/W SOIC 18 pins 3
Junction-to-board characterization parameter ψJB 32.5 °C/W SOIC 18 pins 3
Input current-on VI(on) 2 2.1 V VCE = 1.5 V, IC = 100 mA 4
Input current-on VI(on) 2.2 2.3 V VCE = 1.5 V, IC = 200 mA 4
Collector-emitter saturation voltage VCE(sat) 2 2.1 V VI = 1.8 V, IC = 100 mA 4
Collector-emitter saturation voltage VCE(sat) 3.2 3.3 V VI = 1.8 V, IC = 200 mA 4
Collector-emitter saturation voltage VCE(sat) 1.5 1.6 V VI = 3.3 V, IC = 300 mA 4
Collector-emitter saturation voltage VCE(sat) 1.8 1.9 V VI = 3.3 V, IC = 500 mA 4
Clamp diode forward voltage VF 1.4 1.6 V IF = 350 mA 4
Output leakage current ICEX 50 μA VCE = 18 V, IIN = 0 V 4
Output leakage current ICEX 100 μA VIN = 0 V (Figure 2) 4
Input current IIN 0.6 1.2 mA VIN = 1.8 V, IC = 250 mA 4
Input current IIN 1.6 3 mA VIN = 2.4 V, IC = 250 mA 4
Input current IIN 3.2 4.5 mA VIN = 3.3 V, IC = 250 mA 4
Clamp reverse current IR 100 μA VR = 18 V 4

CAD (KiCad official)

  • Symbol: BULN2803LVS
  • Footprint: Package_SO:SOIC-18W_7.5x11.6mm_P1.27mm
  • 3D model: SOIC-18-300mil (KiCad packages3D, STEP)
  • 3D model files: buln2803lvs-etched.step / buln2803lvs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); buln2803lvs.step / buln2803lvs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: BORN datasheet (7 pp, sha256 a42e279e1b36096f, retrieved 2026-11-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF