component
BUF802IRGTR
Public Made by Adomby adom
Texas Instruments FET Input Amplifiers, VQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownBUF802IRGTR
Texas Instruments · FET Input Amplifiers · VQFN-16(3x3)
BUF802IRGTR from Texas Instruments, in a VQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS+ | power_in | Positive supply connection for the input stage; dual supply range is ±4.5 V to ±6.5 V and VS = (VS+) − (VS−) must not exceed 14 V absolute maximum. |
| 2 | IN | input | Signal input of the JFET input stage, rated for voltages from (VS−) − 0.5 V up to (VS+) V and used directly in buffer mode. |
| 3 | In_Bias | input | JFET bias pin that is used only in composite-loop mode and should be left unconnected in buffer mode. |
| 4 | In_Aux | input | Auxiliary input that controls the output through the auxiliary path in composite-loop mode and should be left unconnected in buffer mode. |
| 5 | VS- | power_in | Negative supply connection for the input stage, internally shorted to pin 8. |
| 6 | Aux_Bias | passive | Must be connected to VS- to enable output control through In_Aux in composite-loop mode. |
| 7 | R_Bias | input | Output-stage bias setting pin; a resistor between R_Bias and VS- sets the quiescent current, with 17.8 kΩ used for the wide-bandwidth test condition. |
| 8 | VS- | power_in | Negative supply connection for the input stage, internally shorted to pin 5. |
| 9 | NC | unconnected | No internal connection. |
| 10 | VSO- | power_in | Negative supply connection for the output stage; must be held at the same potential as VS- because the two are internally tied through back-to-back diodes. |
| 11 | OUT | output | Buffered signal output that drives loads down to 50 Ω, with output voltage limited by the CLH and CLL clamp pins when internal clamps are enabled. |
| 12 | VSO+ | power_in | Positive supply connection for the output stage; must be held at the same potential as VS+ because the two are internally tied through back-to-back diodes. |
| 13 | NC | unconnected | No internal connection. |
| 14 | CLL | input | Sets the negative output clamp voltage and is used only in composite-loop mode; it should be left unconnected in buffer mode, and tying it to VS- disables the internal clamp. |
| 15 | CLH | input | Sets the positive output clamp voltage and is used only in composite-loop mode; it should be left unconnected in buffer mode, and tying it to VS+ disables the internal clamp. |
| 16 | NC | unconnected | No internal connection. |
| 17 | Thermal pad | passive | Thermal pad is electrically isolated from the die and all pins and may be connected to any potential for heat dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16(3x3) |
| Category | Amplifiers/Comparators |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
BUF802IRGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
buf802irgtr-etched.step/buf802irgtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);buf802irgtr.step/buf802irgtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
8030ec533a0ed4d9, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).