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BU8255KVT-E2
Public Made by Adomby adom
ROHM Semicon Serializers / Deserializers, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownBU8255KVT-E2
ROHM Semicon · Serializers / Deserializers · TQFP-64(10x10)
BU8255KVT-E2 from ROHM Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground for the data output driver cells and digital core. |
| 2 | RESERVE | input | Reserved input that must be Low for normal operation. |
| 3 | PD | input | Power-down input: H is normal operation, L is power down with all outputs Low. |
| 4 | OE | input | Output driver enable: H enables outputs, L sets all outputs to Hi-Z. |
| 5 | R/F | input | Output clock edge select: H latches output data on the rising edge, L on the falling edge. |
| 6 | RE6 | output | LVCMOS data output RE6. |
| 7 | RE5 | output | LVCMOS data output RE5. |
| 8 | RE4 | output | LVCMOS data output RE4. |
| 9 | VDD | power_in | 3.3V output driver and digital core supply (recommended 3.0V to 3.6V). |
| 10 | RE3 | output | LVCMOS data output RE3. |
| 11 | RE2 | output | LVCMOS data output RE2. |
| 12 | RE1 | output | LVCMOS data output RE1. |
| 13 | RE0 | output | LVCMOS data output RE0. |
| 14 | RD6 | output | LVCMOS data output RD6. |
| 15 | RD5 | output | LVCMOS data output RD5. |
| 16 | GND | power_in | Ground for the data output driver cells and digital core. |
| 17 | RD4 | output | LVCMOS data output RD4. |
| 18 | RD3 | output | LVCMOS data output RD3. |
| 19 | RD2 | output | LVCMOS data output RD2. |
| 20 | RD1 | output | LVCMOS data output RD1. |
| 21 | RD0 | output | LVCMOS data output RD0. |
| 22 | RC6 | output | LVCMOS data output RC6. |
| 23 | VDD | power_in | 3.3V output driver and digital core supply (recommended 3.0V to 3.6V). |
| 24 | RC5 | output | LVCMOS data output RC5. |
| 25 | RC4 | output | LVCMOS data output RC4. |
| 26 | RC3 | output | LVCMOS data output RC3. |
| 27 | RC2 | output | LVCMOS data output RC2. |
| 28 | RC1 | output | LVCMOS data output RC1. |
| 29 | RC0 | output | LVCMOS data output RC0. |
| 30 | GND | power_in | Ground for the data output driver cells and digital core. |
| 31 | CLKOUT | output | LVCMOS level clock output. |
| 32 | RB6 | output | LVCMOS data output RB6. |
| 33 | RB5 | output | LVCMOS data output RB5. |
| 34 | RB4 | output | LVCMOS data output RB4. |
| 35 | RB3 | output | LVCMOS data output RB3. |
| 36 | RB2 | output | LVCMOS data output RB2. |
| 37 | VDD | power_in | 3.3V output driver and digital core supply (recommended 3.0V to 3.6V). |
| 38 | RB1 | output | LVCMOS data output RB1. |
| 39 | RB0 | output | LVCMOS data output RB0. |
| 40 | RA6 | output | LVCMOS data output RA6. |
| 41 | RA5 | output | LVCMOS data output RA5. |
| 42 | RA4 | output | LVCMOS data output RA4. |
| 43 | RA3 | output | LVCMOS data output RA3. |
| 44 | GND | power_in | Ground for the data output driver cells and digital core. |
| 45 | RA2 | output | LVCMOS data output RA2. |
| 46 | RA1 | output | LVCMOS data output RA1. |
| 47 | RA0 | output | LVCMOS data output RA0. |
| 48 | VDD | power_in | 3.3V output driver and digital core supply (recommended 3.0V to 3.6V). |
| 49 | RA- | input | Negative input of the LVDS data differential pair A. |
| 50 | RA+ | input | Positive input of the LVDS data differential pair A. |
| 51 | RB- | input | Negative input of the LVDS data differential pair B. |
| 52 | RB+ | input | Positive input of the LVDS data differential pair B. |
| 53 | LVDD | power_in | Power supply for the LVDS inputs (recommended 3.0V to 3.6V). |
| 54 | RC- | input | Negative input of the LVDS data differential pair C. |
| 55 | RC+ | input | Positive input of the LVDS data differential pair C. |
| 56 | RCLK- | input | Negative input of the LVDS clock differential pair. |
| 57 | RCLK+ | input | Positive input of the LVDS clock differential pair. |
| 58 | LGND | power_in | Ground for the LVDS inputs. |
| 59 | RD- | input | Negative input of the LVDS data differential pair D. |
| 60 | RD+ | input | Positive input of the LVDS data differential pair D. |
| 61 | RE- | input | Negative input of the LVDS data differential pair E. |
| 62 | RE+ | input | Positive input of the LVDS data differential pair E. |
| 63 | PGND | power_in | Ground for the PLL core. |
| 64 | PVDD | power_in | Power supply for the PLL core (recommended 3.0V to 3.6V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | TQFP-64(10x10) |
| Category | Interface ICs |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.3 | 4 | V | 7 | ||
| Input voltage | VIN | -0.3 | V | max printed as VDD+0.3 | 7 | ||
| Output voltage | VOUT | -0.3 | V | max printed as VDD+0.3 | 7 | ||
| Storage temperature range | Tstg | -55 | 125 | ℃ | 7 | ||
| Package power | PD | 700 | mW | TQFP64V; derating 7.0 mW/℃ at Ta > 25℃ | 7 | ||
| Package power on PCB | PD | 1000 | mW | TQFP64V mounted on PCB 70×70×1.6 mm FR4; derating 10.0 mW/℃ at Ta > 25℃ | 7 | ||
| Supply voltage | VDD | 3 | 3.3 | 3.6 | V | VDD, LVDD, PVDD | 7 |
| Supply noise voltage | VNOZ | 0.1 | V | 7 | |||
| Operating temperature range | Topr | -20 | 85 | ℃ | Clock frequency from 8MHz up to 90MHz | 7 | |
| Operating temperature range | Topr | 0 | 70 | ℃ | Clock frequency from 90MHz up to 112MHz | 7 | |
| Low output voltage | VOL | 0 | 0.4 | V | IOL=4mA (data), IOL=8mA (clock) | 8 | |
| Input current (LVCMOS) | IINC | -10 | 10 | μA | 0V≤VIN≤VDD | 8 | |
| Differential input high threshold | VTH | 100 | mV | VOC=1.2V | 8 | ||
| Differential input low threshold | VTL | -100 | mV | VOC=1.2V | 8 | ||
| Input current (LVDS) | IINL | -25 | 25 | μA | VIN=2.4V / 0V, VDD=3.6V | 8 | |
| Receiver supply current (Gray Scale Pattern) | IRCCG | 52 | mA | fCLKOUT=90MHz CL=8pF, VDD=3.3V | 9 | ||
| Receiver supply current (Worst Case Pattern) | IRCCW | 95 | mA | fCLKOUT=90MHz CL=8pF, VDD=3.3V | 9 | ||
| Receiver power down supply current | IRCCS | 10 | μA | PD=L, OE=L | 9 | ||
| CLKOUT period | tRCP | 8.93 | 125 | ns | 10 | ||
| LVCMOS data rise time | tTLH | 1 | 2 | ns | 10 | ||
| LVCMOS data fall time | tTHL | 1 | 2 | ns | 10 | ||
| Input data position0 | tRIP1 | -0.25 | 0 | 0.25 | ns | 10 | |
| Phase Locked Loop set time | tRPLL | 10 | ms | 10 | |||
| Clock input period | tRCIP | 8.93 | 125 | ns | 10 |
CAD (KiCad official)
- Symbol:
BU8255KVT-E2 - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
bu8255kvt-e2-etched.step/bu8255kvt-e2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bu8255kvt-e2.step/bu8255kvt-e2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (17 pp, sha256
e20dffa918db34c8, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).