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BU8254KVT-E2

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ROHM Semicon LVDS ICs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BU8254KVT-E2

ROHM Semicon · LVDS ICs · TQFP-64(10x10)

BU8254KVT-E2 from ROHM Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TD5 input LVCMOS pixel data input TD5 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
2 GND power_in Ground for LVCMOS inputs and digital core.
3 TD6 input LVCMOS pixel data input TD6 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
4 TE0 input LVCMOS pixel data input TE0 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
5 TE1 input LVCMOS pixel data input TE1 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
6 TE2 input LVCMOS pixel data input TE2 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
7 VDD power_in Power supply for LVCMOS inputs and digital core, 3.0 V to 3.6 V (3.3 V typ).
8 TE3 input LVCMOS pixel data input TE3 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
9 TE4 input LVCMOS pixel data input TE4 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
10 GND power_in Ground for LVCMOS inputs and digital core.
11 TE5 input LVCMOS pixel data input TE5 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
12 CLKIN input Clock input, 8 MHz to 112 MHz (period 8.93 ns to 125 ns).
13 XRST input H: normal operation; L: power down with all outputs Hi-Z.
14 PLLGND power_in Ground for the PLL core.
15 PLLVDD power_in Power supply for the PLL core, 3.0 V to 3.6 V.
16 TE6 input LVCMOS pixel data input TE6 of channel E, with VIH min VDD×0.8 and VIL max VDD×0.2.
17 LVDS GND power_in Ground for LVDS outputs.
18 TEP output LVDS data output positive for channel E.
19 TEN output LVDS data output negative for channel E.
20 TDP output LVDS data output positive for channel D.
21 TDN output LVDS data output negative for channel D.
22 TCLKP output LVDS clock output positive.
23 TCLKN output LVDS clock output negative.
24 TCP output LVDS data output positive for channel C.
25 TCN output LVDS data output negative for channel C.
26 LVDS GND power_in Ground for LVDS outputs.
27 LVDS VDD power_in Power supply for LVDS outputs, 3.0 V to 3.6 V.
28 TBP output LVDS data output positive for channel B.
29 TBN output LVDS data output negative for channel B.
30 TAP output LVDS data output positive for channel A.
31 TAN output LVDS data output negative for channel A.
32 LVDS GND power_in Ground for LVDS outputs.
33 TA0 input LVCMOS pixel data input TA0 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
34 TA1 input LVCMOS pixel data input TA1 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
35 TA2 input LVCMOS pixel data input TA2 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
36 TA3 input LVCMOS pixel data input TA3 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
37 TA4 input LVCMOS pixel data input TA4 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
38 TA5 input LVCMOS pixel data input TA5 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
39 GND power_in Ground for LVCMOS inputs and digital core.
40 TA6 input LVCMOS pixel data input TA6 of channel A, with VIH min VDD×0.8 and VIL max VDD×0.2.
41 TB0 input LVCMOS pixel data input TB0 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
42 TB1 input LVCMOS pixel data input TB1 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
43 RS input LVDS swing select and small-swing VREF input: VDD gives 350 mV swing, GND gives 200 mV swing, 0.6 V to 1.4 V sets VREF for small swing input with 350 mV output.
44 TB2 input LVCMOS pixel data input TB2 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
45 TB3 input LVCMOS pixel data input TB3 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
46 TB4 input LVCMOS pixel data input TB4 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
47 GND power_in Ground for LVCMOS inputs and digital core.
48 TB5 input LVCMOS pixel data input TB5 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
49 TB6 input LVCMOS pixel data input TB6 of channel B, with VIH min VDD×0.8 and VIL max VDD×0.2.
50 TC0 input LVCMOS pixel data input TC0 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
51 VDD power_in Power supply for LVCMOS inputs and digital core, 3.0 V to 3.6 V (3.3 V typ).
52 TC1 input LVCMOS pixel data input TC1 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
53 TC2 input LVCMOS pixel data input TC2 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
54 TC3 input LVCMOS pixel data input TC3 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
55 TC4 input LVCMOS pixel data input TC4 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
56 GND power_in Ground for LVCMOS inputs and digital core.
57 TC5 input LVCMOS pixel data input TC5 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
58 TC6 input LVCMOS pixel data input TC6 of channel C, with VIH min VDD×0.8 and VIL max VDD×0.2.
59 TD0 input LVCMOS pixel data input TD0 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
60 RF input Input clock triggering edge select: H for rising edge, L for falling edge.
61 TD1 input LVCMOS pixel data input TD1 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
62 TD2 input LVCMOS pixel data input TD2 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
63 TD3 input LVCMOS pixel data input TD3 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.
64 TD4 input LVCMOS pixel data input TD4 of channel D, with VIH min VDD×0.8 and VIL max VDD×0.2.

Key specifications

Parameter Value
Manufacturer ROHM Semicon
Package TQFP-64(10x10)
Category Interface ICs
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD -0.3 4 V 6
Storage Temperature Range Tstg -55 125 ℃ 6
Supply Voltage VDD 3 3.3 3.6 V VDD,LVDSVDD,PLLVDD 6
Operating Temperature Range Topr -40 85 ℃ Clock frequency operating from 8MHz up to 90MHz 6
Operating Temperature Range Topr 0 70 ℃ Clock frequency from 90MHz up to 112MHz 6
Small Swing Voltage VDDQ 1.2 2.8 V 7
Input Current IINC -10 10 µA 0V ≤ VIN ≤ VDD 7
Differential Output Voltage, normal swing VOD 250 350 450 mV RS=VDD, RL=100Ω 7
Differential Output Voltage, reduced swing VOD 100 200 300 mV RS=GND, RL=100Ω 7
Change in VOD between complementary output states ΔVOD 35 mV RL=100Ω 7
Common Mode Voltage VOC 1.125 1.25 1.375 V RL=100Ω 7
Change in VOC between complementary output states ΔVOC 35 mV RL=100Ω 7
Output Short Circuit Current IOS -24 mA VOUT=0V, RL=100Ω 7
Output TRI-STATE Current IOZ -10 10 µA XRST=0V, VOUT=0V to VDD 7
Transmitter Power Down Supply Current ITCCS 10 µA XRST=L 8
CLK IN Transition time tTCIT 5 ns 10
CLK IN Period tTCP 8.93 125 ns 10
LVCMOS Data Set up to CLK IN tTS 2.5 ns 10
LVCMOS Data Hold from CLK IN tTH 0 ns 10
LVDS Transition Time tLVT 0.6 1.5 ns 10
Output Data Position 0 tTOP1 -0.2 0 0.2 ns 10
Phase Locked Loop Set Time tTPLL 10 ms 10
Package Power Dissipation TQFP64V 700 mW At Ta ≤ 25℃; de-rating 7.0 mW/℃ above 25℃ 6
Package Power Dissipation TQFP64V on PCB 1000 mW Mounted on 70×70×1.6 mm FR4 PCB; de-rating 10.0 mW/℃ above 25℃ 6
Transmitter Supply Current, Gray Scale, RS=VDD ITCCG 57 mA RL=100Ω,CL=5pF, VDD=3.3V, RS=VDD, Gray Scale Pattern, f=85MHz 8
Transmitter Supply Current, Gray Scale, RS=GND ITCCG 42 mA RL=100Ω,CL=5pF, VDD=3.3V, RS=GND, Gray Scale Pattern, f=85MHz 8
Transmitter Supply Current, Worst Case, RS=VDD ITCCW 62 mA RL=100Ω,CL=5pF, VDD=3.3V, RS=VDD, Worst Case pattern, f=85MHz 8
Transmitter Supply Current, Worst Case, RS=GND ITCCW 45 mA RL=100Ω,CL=5pF, VDD=3.3V, RS=GND, Worst Case pattern, f=85MHz 8

CAD (KiCad official)

  • Symbol: BU8254KVT-E2
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: bu8254kvt-e2-etched.step / bu8254kvt-e2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bu8254kvt-e2.step / bu8254kvt-e2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ROHM Semicon datasheet (20 pp, sha256 2d3a35fc4ad3fc64, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF