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BTS5016-1EKB

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Infineon Technologies Power Distribution Switches, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BTS5016-1EKB

Infineon Technologies · Power Distribution Switches · SOIC-14

BTS5016-1EKB from Infineon Technologies, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected; no internal connection to the chip.
2 NC unconnected Not connected; no internal connection to the chip.
3 GND power_in Ground connection for the device logic; the datasheet states logic ground is independent from load ground.
4 IN input Input signal for channel activation; the input has Schmitt-trigger hysteresis with VIN(L) max 0.8 V and VIN(H) min 2 V, and absolute maximum voltage of -0.3 to 6 V (7 V for t < 2 min) with current limited to ±2 mA.
5 DEN input Diagnostic enable: digital signal that enables or disables the diagnosis of the device; VDEN(L) max 0.8 V, VDEN(H) min 2 V, absolute maximum -0.3 to 6 V (7 V for t < 2 min) with current limited to ±2 mA.
6 IS output Sense current output of the selected channel; the absolute maximum voltage is -0.3 V to VS and the current range is -25 mA to 50 mA.
7 NC unconnected Not connected; no internal connection to the chip.
8 NC unconnected Not connected; no internal connection to the chip.
9 NC unconnected Not connected; no internal connection to the chip.
10 OUT power_out Protected high-side power output channel; all OUT pins must be connected together on the PCB, and the traces must withstand the maximum current that can flow.
11 OUT power_out Protected high-side power output channel; all OUT pins must be connected together on the PCB, and the traces must withstand the maximum current that can flow.
12 OUT power_out Protected high-side power output channel; all OUT pins must be connected together on the PCB, and the traces must withstand the maximum current that can flow.
13 NC unconnected Not connected; no internal connection to the chip.
14 NC unconnected Not connected; no internal connection to the chip.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-14
Category Power Management (PMIC)
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal operating voltage VNOM 8 13.5 18 V 11
Extended operating voltage VS(OP) 5 28 V VIN = 4.5 V, RL = 2 Ω, VDS < 0.5 V 11
Minimum functional supply voltage VS(OP)_MIN 3.8 4.2 5 V VIN = 4.5 V, RL = 2 Ω, From IOUT = 0 A to VDS < 0.5 V 11
Undervoltage shutdown VS(UV) 3 3.4 4.1 V VIN = 4.5 V, VDEN = 0 V, RL = 2 Ω, From VDS < 1 V to IOUT = 0 A 11
Operating current channel active IGND_1 5 9 mA VIN = 5.5 V, VDEN = 5.5 V, Device in RDS(ON), VS = 18 V 11
Standby current for whole device with load IS(OFF) 0.1 0.7 μA VS = 18 V, VOUT = 0 V, VIN floating, VDEN floating, TJ ≤ 85 °C 11
Maximum standby current for whole device with load IS(OFF)_150 6 25 μA VS = 18 V, VOUT = 0 V, VIN floating, VDEN floating, TJ = 150 °C 11
Supply voltage VS -0.3 28 V 9
Reverse polarity voltage -VS(REV) 0 16 V t < 2 min, TA = 25 °C, RL ≥ 2 Ω, RGND = 150 Ω 9
Supply voltage for load dump protection VS(LD) 41 V RI = 2 Ω, RL = 2 Ω 9
Voltage at INPUT pin VIN -0.3 6 V 9
Current through INPUT pin IIN -2 2 mA 9
Voltage at DEN pin VDEN -0.3 6 V 9
Current through DEN pin IDEN -2 2 mA 9
Voltage at IS pin VIS -0.3 V 9
Current through IS pin IIS -25 50 mA 9
Power dissipation (DC) PTOT 2 W TA = 85 °C, TJ < 150 °C 9
Maximum energy dissipation single pulse EAS 95 mJ IL(0) = 8 A, TJ(0) = 150 °C, VS = 13.5 V 9
Voltage at power transistor VDS 41 V 9
Current through ground pin IGND -20 20 mA t < 2 min 10
Junction temperature TJ -40 150 °C 10
Storage temperature TSTG -55 150 °C 10
Drain source diode voltage during reverse polarity VDS(REV) 200 650 700 mV IL = -4 A, TJ = 150 °C 26
Overvoltage protection VS(AZ) 41 46 53 V ISOV = 5 mA 26
Load current limitation IL5(SC) 50 60 80 A VDS = 5 V 26
Thermal shutdown temperature TJ(SC) 150 170 200 °C 26
Open load detection threshold in OFF state VS - VOL(OFF) 4 6 V VIN = 0 V, VDEN = 4.5 V 34
Open load detection threshold in ON state IL(OL) 5.8 35 mA VIN = VDEN = 4.5 V, IIS(OL) = 4 μA 34
IS pin leakage current when sense is disabled IIS_(DIS) 1 μA VIN = 4.5 V, VDEN = 0 V, IL = IL4 = 10 A 34
Sense signal saturation voltage VS - VIS (RANGE) 0 2.2 3 V VIN = 0 V, VOUT = VS > 10 V, VDEN = 4.5 V, IIS = 6 mA 34
Sense signal maximum current in fault condition IIS(FAULT) 6 15 35 mA VIS = VIN = VDSEL = 0 V, VOUT = VS > 10 V, VDEN = 4.5 V 34
Sense pin maximum voltage VIS(AZ) 41 47 53 V IIS = 5 mA 34
Current sense ratio IL0 = 50 mA kILIS0 -50 4000 50 % IL0 = 50 mA, VIN = 4.5 V, VDEN = 4.5 V, TJ = -40 °C; 150 °C 34
Current sense ratio IL1 = 0.5 A kILIS1 -40 3500 40 % IL1 = 0.5 A 34
Current sense ratio IL2 = 2 A kILIS2 -22 3500 22 % IL2 = 2 A 34
Current sense ratio IL3 = 4 A kILIS3 -18 3500 18 % IL3 = 4 A 34
Current sense ratio IL4 = 10 A kILIS4 -17 3500 17 % IL4 = 10 A 34
kILIS derating with current and temperature ΔkILIS -8 0 8 % kILIS3 versus kILIS2 34
Current sense settling time to kILIS stable after positive input slope on both INput and DEN tsIS(ON) 250 μs VDEN = VIN = 0 to 4.5 V, VS = 13.5 V, RIS = 1.2 kΩ, CSENSE < 100 pF, IL = IL3 = 4 A 35
Current sense settling time with load current stable and transition of the DEN tsIS(ON_DEN) 20 μs VIN = 4.5 V, VDEN = 0 to 4.5 V, RIS = 1.2 kΩ, CSENSE < 100 pF, IL = IL3 = 4 A 35
Current sense settling time to IIS stable for overload detection tsIS(FAULT) 250 μs VIN = VDEN = 0 to 4.5 V, RIS = 1.2 kΩ, CSENSE < 100 pF, VDS = 5 V 35
Diagnostic disable time DEN transition to IIS < 50% IL /kILIS tsIS(OFF) 50 μs VIN = 4.5 V, VDEN = 4.5 V to 0 V, RIS = 1.2 kΩ, CSENSE < 100 pF, IL = IL3 = 4 A 35
ON-state resistance per channel RDS(ON)_150 21 28 32 mΩ IL = IL4 = 10 A, VIN = 4.5 V, TJ = 150 °C 19
Drain to source clamping voltage VDS(AZ) 41 46 53 V IDS = 20 mA 19
Output leakage current TJ ≤ 85 °C IL(OFF) 0.1 0.7 μA VIN floating, VOUT = 0 V, TJ ≤ 85 °C 19
Output leakage current TJ = 150 °C IL(OFF)_150 2.5 25 μA VIN floating, VOUT = 0 V, TJ = 150 °C 19
Slew rate 30% to 70% VS dV/dtON 0.1 0.25 0.5 V/μs RL = 2 Ω, VS = 13.5 V 19
Slew rate 70% to 30% VS -dV/dtOFF 0.1 0.25 0.5 V/μs 19
Turn-ON time to VOUT = 90% VS tON 30 100 250 μs 19
Turn-OFF time to VOUT = 10% VS tOFF 30 100 250 μs 19
Low level input voltage range VIN(L) -0.3 0.8 V 37
High level input voltage range VIN(H) 2 6 V 37
Low level input current IIN(L) 1 10 25 μA VIN = 0.8 V 37
High level input current IIN(H) 2 10 25 μA VIN = 5.5 V 37
DEN low level input voltage range VDEN(L) -0.3 0.8 V 37
DEN high level input voltage range VDEN(H) 2 6 V 37
DEN low level input current IDEN(L) 1 10 25 μA VDEN = 0.8 V 37
DEN high level input current IDEN(H) 2 10 25 μA VDEN = 5.5 V 37
Junction to soldering point RthJS 5 K/W Not subject to production test, specified by design 12
Junction to ambient RthJA 30 K/W JEDEC JESD51-2,-5,-7, natural convection, FR4 2s2p board 12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper Cu, 2 x 35 μm Cu). Where applicable, a thermal via array under the exposed pad contacts the first inner copper 12

CAD (KiCad official)

  • Symbol: BTS5016-1EKB
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: bts5016-1ekb-etched.step / bts5016-1ekb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bts5016-1ekb.step / bts5016-1ekb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (53 pp, sha256 2612c1d301a94b7a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF