component
BTS4160DGAXUMA1
Public Made by Adomby adom
Infineon Technologies Power Distribution Switches, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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BTS4160DGAXUMA1
Infineon Technologies · Power Distribution Switches · SOIC-14
BTS4160DGAXUMA1 from Infineon Technologies, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | Battery voltage supply with an operating range of 5.5 V to 20 V, and the overvoltage clamp VS(AZ) is 41 V to 52 V per the electrical characteristics. |
| 2 | GND | power_in | Ground connection for the logic, which is independent from load ground; loss of ground causes the device to turn OFF. |
| 3 | IN0 | input | Input signal for channel 0 that activates the channel on logic high, with VIN(H) at least 2.5 V and VIN(L) at most 1 V. |
| 4 | ST0 | output | Open-drain active-low diagnostic feedback for channel 0 that requires an external pull-up (suggested 15 kΩ) and has VST(LOW) at most 0.6 V. |
| 5 | IN1 | input | Input signal for channel 1 that activates the channel on logic high, with VIN(H) at least 2.5 V and VIN(L) at most 1 V. |
| 6 | ST1 | output | Open-drain active-low diagnostic feedback for channel 1 that requires an external pull-up (suggested 15 kΩ) and has VST(LOW) at most 0.6 V. |
| 7 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
| 8 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
| 9 | OUT1 | power_out | Protected high-side power output of channel 1; all output pins of a channel must be connected together on the PCB. |
| 10 | OUT1 | power_out | Protected high-side power output of channel 1; all output pins of a channel must be connected together on the PCB. |
| 11 | NC | unconnected | Not connected. |
| 12 | OUT0 | power_out | Protected high-side power output of channel 0; all output pins of a channel must be connected together on the PCB. |
| 13 | OUT0 | power_out | Protected high-side power output of channel 0; all output pins of a channel must be connected together on the PCB. |
| 14 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VS | -0.3 | 43 | V | 8 | ||
| Reverse polarity voltage | VS(REV) | 0 | 16 | V | 8 | ||
| Supply voltage for short circuit protection | Vbat(SC) | 0 | 20 | V | RECU = 20mΩ, RCable = 16mΩ/m, LCable = 1µH/m, l = 0 or 5m | 8 | |
| Voltage at INPUT pins | VIN | -10 | 16 | V | 8 | ||
| Current through INPUT pins | IIN | -0.3 | 0.3 | mA | 8 | ||
| Current through ST pin | IST | -5 | 5 | mA | 8 | ||
| Power dissipation (DC), all channels active | PTOT | 0.9 | W | TA = 85°C, Tj < 150°C | 8 | ||
| Maximum switchable inductance, single pulse | EAS | 65 | mJ | IL = 2.9A, VS = 12V | 8 | ||
| Junction temperature | Tj | -40 | 150 | °C | 8 | ||
| Dynamic temperature increase while switching | ΔTj | 60 | K | 8 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 8 | ||
| ESD resistivity IN pin | VESD | -1 | 1 | kV | HBM | 8 | |
| ESD resistivity ST pin | VESD | -4 | 4 | kV | HBM | 8 | |
| ESD resistivity OUT to all other pins shorted | VESD | -5 | 5 | kV | HBM | 8 | |
| Operating voltage | VSOP | 5.5 | 20 | V | VIN = 4.5V, RL = 12Ω, VDS < 0.5V | 9 | |
| Undervoltage switch OFF | VSUV | 4.5 | V | Tj = -40°C, VDS < 0.5V | 9 | ||
| Operating current, one channel active | IGND | 0.9 | mA | One channel active; VIN = 5V | 9 | ||
| Operating current, two channels active | IGND | 1.7 | mA | Two channels active; VIN = 5V | 9 | ||
| Standby current for whole device with load | IS(OFF) | 8 | µA | Tj = 25°C | 9 | ||
| Standby current for whole device with load | IS(OFF) | 12 | µA | Tj = 150°C, VS = 12V, RL = 12Ω, VIN = 0V | 9 | ||
| Junction to soldering point, each channel | RthJSP | 15 | K/W | 9 | |||
| Junction to ambient, one channel active | RthJA | 70 | K/W | with 6cm² cooling area | 9 | ||
| Junction to ambient, two channels active | RthJA | 45 | K/W | with 6cm² cooling area | 9 | ||
| ON-state resistance per channel | RDS(ON) | 260 | 320 | mΩ | Tj = 150°C | 13 | |
| Nominal load current per channel, one channel active | IL(nom) | 1.7 | A | TA = 85°C, Tj < 150°C | 13 | ||
| Nominal load current per channel, two channels active | IL(nom) | 1.2 | A | TA = 85°C, Tj < 150°C | 13 | ||
| Drain to source clamping voltage | VDS(AZ) | 41 | 47 | 52 | V | IDS = 40mA | 13 |
| Output leakage current per channel | IL(OFF) | 1 | 5 | µA | VIN = 0V, VOUT = 0V | 13 | |
| Slew rate ON | dV/dtON | 0.2 | 1 | V/µs | 10% to 30% VS; RL = 12Ω, VS = 12V | 13 | |
| Slew rate OFF | -dV/dtOFF | 0.2 | 1.1 | V/µs | 70% to 40% VS | 13 | |
| Turn-ON time to 90% VS | tON | 100 | 250 | µs | Includes propagation delay | 13 | |
| Turn-OFF time to 10% VS | tOFF | 100 | 270 | µs | Includes propagation delay | 13 | |
| Output leakage current while GND disconnected | IOUT(GND) | 0 | 2 | mA | GND disconnected | 17 | |
| Overvoltage protection | VS(AZ) | 41 | 47 | 52 | V | Is = 40mA | 17 |
| Thermal shutdown temperature | TjSC | 150 | °C | 17 | |||
| Open load detection threshold in OFF state | VOL(OFF) | 1.7 | 2.8 | 4 | V | 20 | |
| Status output (open drain) high level; Zener limit voltage | VST(HIGH) | 5.4 | V | IST = +1.6mA | 20 | ||
| Status output (open drain) low level | VST(LOW) | 0.6 | V | IST = +1.6mA | 20 | ||
| Status change after positive input slope with open load | tdST(ON_OL) | 10 | 20 | µs | 20 | ||
| Status change after positive input slope with overload | tdST(ON_OvL) | 30 | µs | 20 | |||
| Status change after negative input slope with open load | tdST(OFF_OL) | 500 | µs | 21 | |||
| Status change after negative input slope with overload | tdST(OFF_OvL) | 20 | µs | 21 | |||
| Low level input voltage | VIN(L) | 1 | V | 22 | |||
| High level input voltage | VIN(H) | 2.5 | V | 22 | |||
| Low level input current | IIN(L) | 5 | 20 | µA | VIN = 0.4V | 22 | |
| High level input current | IIN(H) | 10 | 60 | µA | VIN = 5V | 22 | |
| Input resistance | RI | 2.5 | 4 | 6 | kΩ | See Figure 16 | 22 |
CAD (KiCad official)
- Symbol:
BTS4160DGAXUMA1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
bts4160dgaxuma1-etched.step/bts4160dgaxuma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bts4160dgaxuma1.step/bts4160dgaxuma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (26 pp, sha256
8978d2f2e3a6cb3c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# BTS4160DGAXUMA1
**Infineon Technologies** · Power Distribution Switches · SOIC-14
BTS4160DGAXUMA1 from Infineon Technologies, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | Battery voltage supply with an operating range of 5.5 V to 20 V, and the overvoltage clamp VS(AZ) is 41 V to 52 V per the electrical characteristics. |
| 2 | GND | power_in | Ground connection for the logic, which is independent from load ground; loss of ground causes the device to turn OFF. |
| 3 | IN0 | input | Input signal for channel 0 that activates the channel on logic high, with VIN(H) at least 2.5 V and VIN(L) at most 1 V. |
| 4 | ST0 | output | Open-drain active-low diagnostic feedback for channel 0 that requires an external pull-up (suggested 15 kΩ) and has VST(LOW) at most 0.6 V. |
| 5 | IN1 | input | Input signal for channel 1 that activates the channel on logic high, with VIN(H) at least 2.5 V and VIN(L) at most 1 V. |
| 6 | ST1 | output | Open-drain active-low diagnostic feedback for channel 1 that requires an external pull-up (suggested 15 kΩ) and has VST(LOW) at most 0.6 V. |
| 7 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
| 8 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
| 9 | OUT1 | power_out | Protected high-side power output of channel 1; all output pins of a channel must be connected together on the PCB. |
| 10 | OUT1 | power_out | Protected high-side power output of channel 1; all output pins of a channel must be connected together on the PCB. |
| 11 | NC | unconnected | Not connected. |
| 12 | OUT0 | power_out | Protected high-side power output of channel 0; all output pins of a channel must be connected together on the PCB. |
| 13 | OUT0 | power_out | Protected high-side power output of channel 0; all output pins of a channel must be connected together on the PCB. |
| 14 | VS | power_in | Battery voltage supply pin, to be wired together with the other VS pins; operating range 5.5 V to 20 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VS | -0.3 | | 43 | V | | 8 |
| Reverse polarity voltage | VS(REV) | 0 | | 16 | V | | 8 |
| Supply voltage for short circuit protection | Vbat(SC) | 0 | | 20 | V | RECU = 20mΩ, RCable = 16mΩ/m, LCable = 1µH/m, l = 0 or 5m | 8 |
| Voltage at INPUT pins | VIN | -10 | | 16 | V | | 8 |
| Current through INPUT pins | IIN | -0.3 | | 0.3 | mA | | 8 |
| Current through ST pin | IST | -5 | | 5 | mA | | 8 |
| Power dissipation (DC), all channels active | PTOT | | | 0.9 | W | TA = 85°C, Tj < 150°C | 8 |
| Maximum switchable inductance, single pulse | EAS | | | 65 | mJ | IL = 2.9A, VS = 12V | 8 |
| Junction temperature | Tj | -40 | | 150 | °C | | 8 |
| Dynamic temperature increase while switching | ΔTj | | | 60 | K | | 8 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 8 |
| ESD resistivity IN pin | VESD | -1 | | 1 | kV | HBM | 8 |
| ESD resistivity ST pin | VESD | -4 | | 4 | kV | HBM | 8 |
| ESD resistivity OUT to all other pins shorted | VESD | -5 | | 5 | kV | HBM | 8 |
| Operating voltage | VSOP | 5.5 | | 20 | V | VIN = 4.5V, RL = 12Ω, VDS < 0.5V | 9 |
| Undervoltage switch OFF | VSUV | | | 4.5 | V | Tj = -40°C, VDS < 0.5V | 9 |
| Operating current, one channel active | IGND | | | 0.9 | mA | One channel active; VIN = 5V | 9 |
| Operating current, two channels active | IGND | | | 1.7 | mA | Two channels active; VIN = 5V | 9 |
| Standby current for whole device with load | IS(OFF) | | | 8 | µA | Tj = 25°C | 9 |
| Standby current for whole device with load | IS(OFF) | | | 12 | µA | Tj = 150°C, VS = 12V, RL = 12Ω, VIN = 0V | 9 |
| Junction to soldering point, each channel | RthJSP | | | 15 | K/W | | 9 |
| Junction to ambient, one channel active | RthJA | | | 70 | K/W | with 6cm² cooling area | 9 |
| Junction to ambient, two channels active | RthJA | | | 45 | K/W | with 6cm² cooling area | 9 |
| ON-state resistance per channel | RDS(ON) | | 260 | 320 | mΩ | Tj = 150°C | 13 |
| Nominal load current per channel, one channel active | IL(nom) | 1.7 | | | A | TA = 85°C, Tj < 150°C | 13 |
| Nominal load current per channel, two channels active | IL(nom) | 1.2 | | | A | TA = 85°C, Tj < 150°C | 13 |
| Drain to source clamping voltage | VDS(AZ) | 41 | 47 | 52 | V | IDS = 40mA | 13 |
| Output leakage current per channel | IL(OFF) | | 1 | 5 | µA | VIN = 0V, VOUT = 0V | 13 |
| Slew rate ON | dV/dtON | 0.2 | | 1 | V/µs | 10% to 30% VS; RL = 12Ω, VS = 12V | 13 |
| Slew rate OFF | -dV/dtOFF | 0.2 | | 1.1 | V/µs | 70% to 40% VS | 13 |
| Turn-ON time to 90% VS | tON | | 100 | 250 | µs | Includes propagation delay | 13 |
| Turn-OFF time to 10% VS | tOFF | | 100 | 270 | µs | Includes propagation delay | 13 |
| Output leakage current while GND disconnected | IOUT(GND) | 0 | | 2 | mA | GND disconnected | 17 |
| Overvoltage protection | VS(AZ) | 41 | 47 | 52 | V | Is = 40mA | 17 |
| Thermal shutdown temperature | TjSC | 150 | | | °C | | 17 |
| Open load detection threshold in OFF state | VOL(OFF) | 1.7 | 2.8 | 4 | V | | 20 |
| Status output (open drain) high level; Zener limit voltage | VST(HIGH) | 5.4 | | | V | IST = +1.6mA | 20 |
| Status output (open drain) low level | VST(LOW) | | | 0.6 | V | IST = +1.6mA | 20 |
| Status change after positive input slope with open load | tdST(ON_OL) | | 10 | 20 | µs | | 20 |
| Status change after positive input slope with overload | tdST(ON_OvL) | 30 | | | µs | | 20 |
| Status change after negative input slope with open load | tdST(OFF_OL) | | | 500 | µs | | 21 |
| Status change after negative input slope with overload | tdST(OFF_OvL) | | | 20 | µs | | 21 |
| Low level input voltage | VIN(L) | | | 1 | V | | 22 |
| High level input voltage | VIN(H) | 2.5 | | | V | | 22 |
| Low level input current | IIN(L) | 5 | | 20 | µA | VIN = 0.4V | 22 |
| High level input current | IIN(H) | 10 | | 60 | µA | VIN = 5V | 22 |
| Input resistance | RI | 2.5 | 4 | 6 | kΩ | See Figure 16 | 22 |
## CAD (KiCad official)
- Symbol: `BTS4160DGAXUMA1`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `bts4160dgaxuma1-etched.step` / `bts4160dgaxuma1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bts4160dgaxuma1.step` / `bts4160dgaxuma1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588927305766866944) (26 pp, sha256 `8978d2f2e3a6cb3c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/bts4160dgaxuma1-datasheet.pdf)