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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	bts3046sdratma1: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plai… · Ray	25d ago
viewers	bts3046sdratma1: viewers · Ray	2mo ago
bts3046sdratma1-etched.fit.json	bts3046sdratma1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bts3046sdratma1-etched.glb	bts3046sdratma1: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plai… · Ray	25d ago
bts3046sdratma1-etched.step	bts3046sdratma1: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plai… · Ray	25d ago
bts3046sdratma1.glb	Publish 0.1.0 · Ray	2mo ago
bts3046sdratma1.kicad_mod	Publish 0.1.0 · Ray	2mo ago
bts3046sdratma1.kicad_sym	Publish 0.1.0 · Ray	2mo ago
bts3046sdratma1.lbr	Publish 0.1.0 · Ray	2mo ago
bts3046sdratma1.step	Publish 0.1.0 · Ray	2mo ago
package.json	Publish 0.1.0 · Ray	2mo ago
page.json	bts3046sdratma1: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plai… · Ray	25d ago
README.md	bts3046sdratma1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago

BTS3046SDRATMA1

Infineon Technologies · Power Distribution Switches · TO-252

BTS3046SDRATMA1 from Infineon Technologies, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	input	Logic-level gate/control input (VIN(ON) 2 V-10 V functional range, IIN(ON) ≤ 30 µA in normal operation). Compatible with 3.3 V/5 V logic and also supports analog drive. Also serves as a bi-directional fault-feedback node: on internal fault the pin sinks up to IIN(lim) ≈ 400 µA, pulling an external series resistor to signal the fault to the driving MCU. Input current is internally self-limited between −0.2 V and 10 V and clamped to ±2 mA outside that window.
2	Drain	power_in	Drain of the internal N-channel power DMOS; connects to the load return that goes to Vbat (low-side switching). Rated for VD up to 60 V active-clamped; functional drain voltage 2.5 V-36 V. Nominal load current 3.6 A, current limit ≥ 10 A. Electrically common with the exposed tab (pin 4).
3	Source	power_in	Source of the internal power DMOS; the module/board GND reference. All voltages in the datasheet are referenced to this pin; ESD HBM rating (±2 kV) is specified with Source tied to ground.
4	Drain	power_in	Exposed thermal tab, electrically the Drain (common with pin 2). Provides the primary heat-sinking path; RthJC ≈ 0.9 K/W, RthJA(2s2p) ≈ 27 K/W on a JESD51 2s2p board. Solder to a copper pour connected to the load return for thermal performance.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	TO-252
Category	Power Management (PMIC)
Pins	4

Ordering variants

Same part, different packaging or reel option.

BTS3046SDRATMA1

CAD (KiCad official)

Symbol: BTS3046SDRATMA1
Footprint: Package_TO_SOT_SMD:TO-252-2
3D model: TO-252 (KiCad packages3D, STEP)
3D model files: bts3046sdratma1-etched.step / bts3046sdratma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bts3046sdratma1.step / bts3046sdratma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (None pp, sha256 b678104907d6c0a1, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF