component

BST52

Public Made by Adom

by adom

Nexperia Darlington Transistors, SOT-89-3. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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docs bst52: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers bst52: viewers · Ray 1mo ago
bst52-etched.fit.json bst52: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bst52-etched.glb bst52: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bst52-etched.step bst52: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bst52.glb Publish 0.1.0 · Ray 1mo ago
bst52.kicad_mod Publish 0.1.0 · Ray 1mo ago
bst52.kicad_sym Publish 0.1.0 · Ray 1mo ago
bst52.lbr Publish 0.1.0 · Ray 1mo ago
bst52.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json bst52: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md bst52: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

BST52

Nexperia · Darlington Transistors · SOT-89-3

BST52 from Nexperia, in a SOT-89-3. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E passive Emitter of the NPN Darlington pair. Common return path for collector current; VEBO limited to 5 V (open collector).
2 C passive Collector of the NPN Darlington pair. Main current-handling terminal; VCEO up to 80 V, IC up to 1 A (peak 2 A). Also connected to the SOT89 heat-spreading tab for improved thermal dissipation.
3 B passive Base control input of the NPN Darlington pair. Drives the compound transistor through an integrated base-emitter resistor with an anti-parallel diode; IB limited to 100 mA.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-89-3
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: BST52
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89-3 (KiCad packages3D, STEP)
  • 3D model files: bst52-etched.step / bst52-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bst52.step / bst52.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (8 pp, sha256 8ca616767aa12634, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF