BR4953D-A

{
  "slug": "br4953d-a",
  "version": "0.1.0",
  "type": "component",
  "description": "Foshan Blue Rocket Elec MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "transistors-thyristors",
    "br4953d-a",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "br4953d-a.kicad_sym",
    "br4953d-a.kicad_mod",
    "br4953d-a.glb",
    "br4953d-a.step",
    "br4953d-a.lbr",
    "docs/hero.png",
    "docs/br4953d-a-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "br4953d-a-hero.glb",
    "br4953d-a-hero.overlay.json",
    "br4953d-a-etched.glb"
  ],
  "component": {
    "mpn": "BR4953D-A",
    "manufacturer": "Foshan Blue Rocket Elec",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884247269036032",
    "parts": {
      "symbol": "br4953d-a.kicad_sym",
      "footprint": "br4953d-a.kicad_mod",
      "model_3d": "br4953d-a-hero.glb",
      "model_3d_plain": "br4953d-a-etched.glb",
      "model_3d_step": "br4953d-a-etched.step",
      "model_3d_step_plain": "br4953d-a.step",
      "lbr": "br4953d-a.lbr"
    },
    "distributor_links": {
      "lcsc": "C328565"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T02:18:11Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "S1",
        "type": "passive",
        "description": "Source terminal of P-channel MOSFET 1; the datasheet gives no pin-specific limit, and the device ratings are VDSS -20 V and VGSS ±12 V."
      },
      {
        "number": "2",
        "name": "G1",
        "type": "input",
        "description": "Gate terminal of P-channel MOSFET 1; the gate-source voltage is rated at ±12 V (VGSS) in the absolute maximum ratings."
      },
      {
        "number": "3",
        "name": "S2",
        "type": "passive",
        "description": "Source terminal of P-channel MOSFET 2; the datasheet gives no pin-specific limit, and the device ratings are VDSS -20 V and VGSS ±12 V."
      },
      {
        "number": "4",
        "name": "G2",
        "type": "input",
        "description": "Gate terminal of P-channel MOSFET 2; the gate-source voltage is rated at ±12 V (VGSS) in the absolute maximum ratings."
      },
      {
        "number": "5",
        "name": "D2",
        "type": "passive",
        "description": "Drain terminal of P-channel MOSFET 2, internally paired with pin 6; the drain-source voltage is rated at -20 V (VDSS)."
      },
      {
        "number": "6",
        "name": "D2",
        "type": "passive",
        "description": "Drain terminal of P-channel MOSFET 2, internally paired with pin 5; the drain-source voltage is rated at -20 V (VDSS)."
      },
      {
        "number": "7",
        "name": "D1",
        "type": "passive",
        "description": "Drain terminal of P-channel MOSFET 1, internally paired with pin 8; the drain-source voltage is rated at -20 V (VDSS)."
      },
      {
        "number": "8",
        "name": "D1",
        "type": "passive",
        "description": "Drain terminal of P-channel MOSFET 1, internally paired with pin 7; the drain-source voltage is rated at -20 V (VDSS)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN suffix '-A' is not a separate package variant in this datasheet. Per the marking instruction; The datasheet lists the pin assignments only in the pinning table on page 1 (PIN1 S1 ... PIN8 D1). I; Packaging table (page 7) lists the package as 'SOP/ESOP-8'. The package outline drawing on page 5 is"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0242,
        "at": "2026-10-19T02:17:53"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884247269036032",
        "pages": 7,
        "sha256": "0aa231a2604eb07a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "br4953d-a-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "419cdd83f1a35fb0078f6af63f4784607a9d3afa44af38f6d5f584764e3243aa",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}