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BR25H080FJ-2CE2

Public Made by Adom

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ROHM Semicon EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BR25H080FJ-2CE2

ROHM Semicon · EEPROM · SOIC-8

BR25H080FJ-2CE2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CSB input Chip select input; set LOW to start a command, as described for the read and write command cycles.
2 SO output Serial data output, shifted out on the falling edge of SCK starting from the MSB.
3 WPB input Write protect input; when LOW it prohibits the write status register command, but only when the WPEN bit is set to 1.
4 GND power_in Input/output reference voltage, 0 V.
5 SI input Start bit, op code, address and serial data input, latched on the rising edge of SCK starting from the MSB.
6 SCK input Serial clock input, up to 10 MHz (max).
7 HOLDB input Hold input; when driven LOW while SCK is LOW, command communication is suspended temporarily (HOLD status).
8 VCC power_in Power supply, 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer ROHM Semicon
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.3 6.5 V Ta=25°C 2
Permissible Dissipation (SOP-J8) Pd 560 mW Ta=25°C; SOP-J8 (*4); 4.5mW per 1°C reduction when Ta≥25°C 2
Storage Temperature Range Tstg -65 150 °C 2
Operating Temperature Range Topr -40 125 °C 2
Terminal Voltage -0.3 V 2
Supply Voltage VCC 2.5 5.5 V 2
Input Voltage Vin 0 V 2
Write Cycles 1e+06 Cycles Ta≦85°C 2
Write Cycles 500000 Cycles Ta≦105°C 2
Write Cycles 300000 Cycles Ta≦125°C 2
Data Retention 100 Years Ta≦25°C 2
Data Retention 60 Years Ta≦105°C 2
Data Retention 50 Years Ta≦125°C 2
Input Capacity CIN 8 pF Ta=25°C, frequency=5MHz, VIN=GND 2
Output Capacity COUT 8 pF Ta=25°C, frequency=5MHz, VOUT=GND 2
Input Low Voltage VIL -0.3 V 2.5V≦VCC≦5.5V 3
Output Low Voltage VOL 0 0.4 V IOL=2.1mA 3
Input Leakage Current ILI -2 2 μA VIN=0V to VCC 3
Output Leakage Current ILO -2 2 μA VOUT=0V to VCC, CSB=VCC 3
Supply Current (WRITE) ICC1 2 mA VCC=2.5V, fSCK=5MHz, tE/W=4ms; VIH/VIL=0.9VCC/0.1VCC, SO=OPEN; Byte write, Page write, Write status register 3
Supply Current (WRITE) ICC2 3 mA VCC=5.5V, fSCK=5 or 10 MHz, tE/W=4ms; VIH/VIL=0.9VCC/0.1VCC, SO=OPEN; Byte write, Page write, Write status register 3
Supply Current (READ) ICC3 1.5 mA VCC=2.5V, fSCK=5MHz; VIH/VIL=0.9VCC/0.1VCC, SO=OPEN; Read, Read status register 3
Supply Current (READ) ICC4 2 mA VCC=5.5V, fSCK=5MHz; VIH/VIL=0.9VCC/0.1VCC, SO=OPEN; Read, Read status register 3
Supply Current (READ) ICC5 4 mA VCC=5.5V, fSCK=10MHz; VIH/VIL=0.9VCC/0.1VCC, SO=OPEN; Read, Read status register 3
Standby Current ISB 10 μA VCC=5.5V; CSB=HOLDB=WPB=VCC, SCK=SI=VCC or =GND, SO=OPEN 3
SCK Frequency fSCK 5 MHz 2.5V≦VCC≦5.5V; CL1=100pF 4
SCK High Time tSCKWH 85 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SCK Low Time tSCKWL 85 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
CSB High Time tCS 85 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
CSB Setup Time tCSS 90 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
CSB Hold Time tCSH 85 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SCK Setup Time tSCKS 90 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SCK Hold Time tSCKH 90 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SI Setup Time tDIS 20 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SI Hold Time tDIH 30 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
Data Output Delay Time1 tPD1 60 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
Data Output Delay Time2 tPD2 50 ns 2.5V≦VCC≦5.5V; CL2=30pF 4
Output Hold Time tOH 0 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
Output Disable Time tOZ 100 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
HOLDB Setting Setup Time tHFS 0 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
HOLDB Setting Hold Time tHFH 40 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
HOLDB Release Setup Time tHRS 0 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
HOLDB Release Hold Time tHRH 70 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
Time from HOLDB to Output High-Z tHOZ 100 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
Time from HOLDB to Output Change tHPD 60 ns 2.5V≦VCC≦5.5V; CL1=100pF 4
SCK Rise Time tRC 1 μs 2.5V≦VCC≦5.5V; not 100% tested 4
SCK Fall Time tFC 1 μs 2.5V≦VCC≦5.5V; not 100% tested 4
OUTPUT Rise Time tRO 40 ns 2.5V≦VCC≦5.5V; not 100% tested 4
OUTPUT Fall Time tFO 40 ns 2.5V≦VCC≦5.5V; not 100% tested 4
Write Time tE/W 4 ms 2.5V≦VCC≦5.5V 4
Maximum junction temperature Tjmax 150 °C 25

CAD (KiCad official)

  • Symbol: BR25H080FJ-2CE2
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: br25h080fj-2ce2-etched.step / br25h080fj-2ce2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); br25h080fj-2ce2.step / br25h080fj-2ce2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ROHM Semicon datasheet (35 pp, sha256 0b2c3b5375aa2597, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF