component
BR24L16FJ-WE2
Public Made by Adomby adom
ROHM Semicon Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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BR24L16FJ-WE2
ROHM Semicon · Pre-ordered Chips · SOIC-8
BR24L16FJ-WE2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Slave address setting pin, but for the BR24L16-W it is not connected (N.C.). |
| 2 | A1 | input | Slave address setting pin, but for the BR24L16-W it is not connected (N.C.). |
| 3 | A2 | input | Slave address setting pin, but for the BR24L16-W it is marked Don't Use in the pin configuration footnote. |
| 4 | GND | power_in | Reference voltage for all inputs and outputs, 0V. |
| 5 | SDA | bidirectional | Serial data terminal carrying the slave and word address and serial data input and output. |
| 6 | SCL | input | Serial clock input; inputs are read on the SCL rising edge and data is output in sync with the SCL falling edge. |
| 7 | WP | input | Write protect input: set LOW from the first data bit D0 clock rise until tWR to execute a write, and set HIGH to cancel the write (a write in progress is forcibly ended and the addressed data is not guaranteed). |
| 8 | Vcc | power_in | Power supply input; the datasheet specifies 1.7V to 5.5V for the BR24L16-W. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH input voltage 1 (min 0.7Vcc; max Vcc+1.0) | VIH1 | 0.7 | 1 | V | 2.5≦Vcc≦5.5V; bounds printed relative to Vcc (min 0.7Vcc, max Vcc+1.0); *2 BR24L16/32-W | 2 | |
| LOW input voltage 1 (max 0.3Vcc) | VIL1 | -0.3 | 0.3 | V | 2.5≦Vcc≦5.5V; max printed as 0.3Vcc; *2 BR24L16/32-W | 2 | |
| HIGH input voltage 2 (min 0.8Vcc; max Vcc+1.0) | VIH2 | 0.8 | 1 | V | 1.8≦Vcc＜2.5V; bounds printed relative to Vcc (min 0.8Vcc, max Vcc+1.0); *2 BR24L16/32-W | 2 | |
| LOW input voltage 2 (max 0.2Vcc) | VIL2 | -0.3 | 0.2 | V | 1.8≦Vcc＜2.5V; max printed as 0.2Vcc; *2 BR24L16/32-W | 2 | |
| HIGH input voltage 3 (*3 BR24L02/16-W; min 0.8Vcc; max Vcc+1.0) | VIH3 | 0.8 | 1 | V | 1.7≦Vcc＜1.8V; bounds printed relative to Vcc (min 0.8Vcc, max Vcc+1.0) | 2 | |
| LOW input voltage 3 (*2 BR24L16/32-W; max 0.1Vcc) | VIL3 | -0.3 | 0.1 | V | 1.7≦Vcc＜1.8V; max printed as 0.1Vcc | 2 | |
| LOW output voltage 1 (SDA) | VOL1 | 0.4 | V | IOL=3.0mA, 2.5V≦Vcc≦5.5V, (SDA) | 2 | ||
| LOW output voltage 2 (SDA) | VOL2 | 0.2 | V | IOL=0.7mA, 1.7V≦Vcc＜2.5V, (SDA) | 2 | ||
| Input leak current | ILI | -1 | 1 | μA | VIN=0V to Vcc | 2 | |
| Output leak current (SDA) | ILO | -1 | 1 | μA | VOUT=0V to Vcc, (SDA) | 2 | |
| Current consumption at byte write, page write action (*5 BR24L01A/02/04/08/16-W) | ICC1 | 2 | mA | Vcc=5.5V,fSCL=400kHz, tWR=5ms | 2 | ||
| Current consumption at random read, current read, sequential read | ICC2 | 0.5 | mA | Vcc=5.5V,fSCL=400kHz | 2 | ||
| Standby current | ISB | 2 | μA | Vcc=5.5V, SDA・SCL=Vcc, A0, A1, A2=GND, WP=GND | 2 | ||
| Supply voltage (absolute maximum) | VCC | -0.3 | 6.5 | V | 2 | ||
| Power dissipation, SOP-J8 package | Pd | 450 | mW | SOP-J8; when using at Ta=25℃ or higher, 4.5mW to be reduced per 1℃ | 2 | ||
| Storage temperature | Tstg | -65 | 125 | ℃ | 2 | ||
| Operating temperature | Topr | -40 | 85 | ℃ | 2 | ||
| Terminal voltage (max printed as Vcc+1.0) | -0.3 | 1 | V | max printed as Vcc+1.0 (relative to Vcc) | 2 | ||
| Power source voltage (recommended; footnote *1 BR24L02/16/32-W: 1.7V to 5.5V) | Vcc | 1.7 | 5.5 | V | BR24L02/16/32-W per footnote *1; series table prints 1.8 to 5.5 | 2 | |
| Input voltage (upper limit printed as Vcc) | VIN | 0 | V | upper limit printed as Vcc | 2 | ||
| Number of data rewrite times | 1e+06 | Times | Ta=25℃, Vcc=1.8V to 5.5V (*1 BR24L02/16/32-W: 1.7V to 5.5V); *2 not 100% tested | 2 | |||
| Data hold years | 40 | Years | Ta=25℃, Vcc=1.8V to 5.5V (*1 BR24L02/16/32-W: 1.7V to 5.5V); *2 not 100% tested | 2 | |||
| SCL frequency (FAST-MODE) | fSCL | 400 | kHz | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| SCL frequency (STANDARD-MODE) | fSCL | 100 | kHz | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Data clock HIGH time (FAST-MODE) | tHIGH | 0.6 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Data clock HIGH time (STANDARD-MODE) | tHIGH | 4 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Data clock LOW time (FAST-MODE) | tLOW | 1.2 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Data clock LOW time (STANDARD-MODE) | tLOW | 4.7 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| SDA, SCL rise time (FAST-MODE; *2 not 100% tested) | tR | 0.3 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| SDA, SCL rise time (STANDARD-MODE; *2 not 100% tested) | tR | 1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| SDA, SCL fall time (FAST-MODE; *2 not 100% tested) | tF | 0.3 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| SDA, SCL fall time (STANDARD-MODE; *2 not 100% tested) | tF | 0.3 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Start condition hold time (FAST-MODE) | tHD:STA | 0.6 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Start condition hold time (STANDARD-MODE) | tHD:STA | 4 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Start condition setup time (FAST-MODE) | tSU:STA | 0.6 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Start condition setup time (STANDARD-MODE) | tSU:STA | 4.7 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Input data hold time (FAST-MODE) | tHD:DAT | 0 | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Input data hold time (STANDARD-MODE) | tHD:DAT | 0 | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Input data setup time (FAST-MODE) | tSU:DAT | 100 | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Input data setup time (STANDARD-MODE) | tSU:DAT | 250 | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Output data delay time (FAST-MODE) | tPD | 0.1 | 0.9 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | |
| Output data delay time (STANDARD-MODE) | tPD | 0.2 | 3.5 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | |
| Output data hold time (FAST-MODE) | tDH | 0.1 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Output data hold time (STANDARD-MODE) | tDH | 0.2 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Stop condition setup time (FAST-MODE) | tSU:STO | 0.6 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Stop condition setup time (STANDARD-MODE) | tSU:STO | 4.7 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Bus release time before transfer start (FAST-MODE) | tBUF | 1.2 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Bus release time before transfer start (STANDARD-MODE) | tBUF | 4.7 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Internal write cycle time (FAST-MODE) | tWR | 5 | ms | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Internal write cycle time (STANDARD-MODE) | tWR | 5 | ms | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| Noise removal valid period, SDA and SCL terminal (FAST-MODE) | tI | 0.1 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| Noise removal valid period, SDA and SCL terminal (STANDARD-MODE) | tI | 0.1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| WP hold time (FAST-MODE) | tHD:WP | 0 | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| WP hold time (STANDARD-MODE) | tHD:WP | 0 | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| WP setup time (FAST-MODE) | tSU:WP | 0.1 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| WP setup time (STANDARD-MODE) | tSU:WP | 0.1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 | ||
| WP valid time (FAST-MODE) | tHIGH:WP | 1 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 | ||
| WP valid time (STANDARD-MODE) | tHIGH:WP | 1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
CAD (KiCad official)
- Symbol:
BR24L16FJ-WE2 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
br24l16fj-we2-etched.step/br24l16fj-we2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);br24l16fj-we2.step/br24l16fj-we2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (39 pp, sha256
7f7d69eca6c5c3aa, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# BR24L16FJ-WE2
**ROHM Semicon** · Pre-ordered Chips · SOIC-8
BR24L16FJ-WE2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Slave address setting pin, but for the BR24L16-W it is not connected (N.C.). |
| 2 | A1 | input | Slave address setting pin, but for the BR24L16-W it is not connected (N.C.). |
| 3 | A2 | input | Slave address setting pin, but for the BR24L16-W it is marked Don't Use in the pin configuration footnote. |
| 4 | GND | power_in | Reference voltage for all inputs and outputs, 0V. |
| 5 | SDA | bidirectional | Serial data terminal carrying the slave and word address and serial data input and output. |
| 6 | SCL | input | Serial clock input; inputs are read on the SCL rising edge and data is output in sync with the SCL falling edge. |
| 7 | WP | input | Write protect input: set LOW from the first data bit D0 clock rise until tWR to execute a write, and set HIGH to cancel the write (a write in progress is forcibly ended and the addressed data is not guaranteed). |
| 8 | Vcc | power_in | Power supply input; the datasheet specifies 1.7V to 5.5V for the BR24L16-W. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH input voltage 1 (min 0.7Vcc; max Vcc+1.0) | VIH1 | 0.7 | | 1 | V | 2.5≦Vcc≦5.5V; bounds printed relative to Vcc (min 0.7Vcc, max Vcc+1.0); *2 BR24L16/32-W | 2 |
| LOW input voltage 1 (max 0.3Vcc) | VIL1 | -0.3 | | 0.3 | V | 2.5≦Vcc≦5.5V; max printed as 0.3Vcc; *2 BR24L16/32-W | 2 |
| HIGH input voltage 2 (min 0.8Vcc; max Vcc+1.0) | VIH2 | 0.8 | | 1 | V | 1.8≦Vcc＜2.5V; bounds printed relative to Vcc (min 0.8Vcc, max Vcc+1.0); *2 BR24L16/32-W | 2 |
| LOW input voltage 2 (max 0.2Vcc) | VIL2 | -0.3 | | 0.2 | V | 1.8≦Vcc＜2.5V; max printed as 0.2Vcc; *2 BR24L16/32-W | 2 |
| HIGH input voltage 3 (*3 BR24L02/16-W; min 0.8Vcc; max Vcc+1.0) | VIH3 | 0.8 | | 1 | V | 1.7≦Vcc＜1.8V; bounds printed relative to Vcc (min 0.8Vcc, max Vcc+1.0) | 2 |
| LOW input voltage 3 (*2 BR24L16/32-W; max 0.1Vcc) | VIL3 | -0.3 | | 0.1 | V | 1.7≦Vcc＜1.8V; max printed as 0.1Vcc | 2 |
| LOW output voltage 1 (SDA) | VOL1 | | | 0.4 | V | IOL=3.0mA, 2.5V≦Vcc≦5.5V, (SDA) | 2 |
| LOW output voltage 2 (SDA) | VOL2 | | | 0.2 | V | IOL=0.7mA, 1.7V≦Vcc＜2.5V, (SDA) | 2 |
| Input leak current | ILI | -1 | | 1 | μA | VIN=0V to Vcc | 2 |
| Output leak current (SDA) | ILO | -1 | | 1 | μA | VOUT=0V to Vcc, (SDA) | 2 |
| Current consumption at byte write, page write action (*5 BR24L01A/02/04/08/16-W) | ICC1 | | | 2 | mA | Vcc=5.5V,fSCL=400kHz, tWR=5ms | 2 |
| Current consumption at random read, current read, sequential read | ICC2 | | | 0.5 | mA | Vcc=5.5V,fSCL=400kHz | 2 |
| Standby current | ISB | | | 2 | μA | Vcc=5.5V, SDA・SCL=Vcc, A0, A1, A2=GND, WP=GND | 2 |
| Supply voltage (absolute maximum) | VCC | -0.3 | | 6.5 | V | | 2 |
| Power dissipation, SOP-J8 package | Pd | | | 450 | mW | SOP-J8; when using at Ta=25℃ or higher, 4.5mW to be reduced per 1℃ | 2 |
| Storage temperature | Tstg | -65 | | 125 | ℃ | | 2 |
| Operating temperature | Topr | -40 | | 85 | ℃ | | 2 |
| Terminal voltage (max printed as Vcc+1.0) | | -0.3 | | 1 | V | max printed as Vcc+1.0 (relative to Vcc) | 2 |
| Power source voltage (recommended; footnote *1 BR24L02/16/32-W: 1.7V to 5.5V) | Vcc | 1.7 | | 5.5 | V | BR24L02/16/32-W per footnote *1; series table prints 1.8 to 5.5 | 2 |
| Input voltage (upper limit printed as Vcc) | VIN | 0 | | | V | upper limit printed as Vcc | 2 |
| Number of data rewrite times | | 1e+06 | | | Times | Ta=25℃, Vcc=1.8V to 5.5V (*1 BR24L02/16/32-W: 1.7V to 5.5V); *2 not 100% tested | 2 |
| Data hold years | | 40 | | | Years | Ta=25℃, Vcc=1.8V to 5.5V (*1 BR24L02/16/32-W: 1.7V to 5.5V); *2 not 100% tested | 2 |
| SCL frequency (FAST-MODE) | fSCL | | | 400 | kHz | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| SCL frequency (STANDARD-MODE) | fSCL | | | 100 | kHz | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Data clock HIGH time (FAST-MODE) | tHIGH | 0.6 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Data clock HIGH time (STANDARD-MODE) | tHIGH | 4 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Data clock LOW time (FAST-MODE) | tLOW | 1.2 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Data clock LOW time (STANDARD-MODE) | tLOW | 4.7 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| SDA, SCL rise time (FAST-MODE; *2 not 100% tested) | tR | | | 0.3 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| SDA, SCL rise time (STANDARD-MODE; *2 not 100% tested) | tR | | | 1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| SDA, SCL fall time (FAST-MODE; *2 not 100% tested) | tF | | | 0.3 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| SDA, SCL fall time (STANDARD-MODE; *2 not 100% tested) | tF | | | 0.3 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Start condition hold time (FAST-MODE) | tHD:STA | 0.6 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Start condition hold time (STANDARD-MODE) | tHD:STA | 4 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Start condition setup time (FAST-MODE) | tSU:STA | 0.6 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Start condition setup time (STANDARD-MODE) | tSU:STA | 4.7 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Input data hold time (FAST-MODE) | tHD:DAT | 0 | | | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Input data hold time (STANDARD-MODE) | tHD:DAT | 0 | | | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Input data setup time (FAST-MODE) | tSU:DAT | 100 | | | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Input data setup time (STANDARD-MODE) | tSU:DAT | 250 | | | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Output data delay time (FAST-MODE) | tPD | 0.1 | | 0.9 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Output data delay time (STANDARD-MODE) | tPD | 0.2 | | 3.5 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Output data hold time (FAST-MODE) | tDH | 0.1 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Output data hold time (STANDARD-MODE) | tDH | 0.2 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Stop condition setup time (FAST-MODE) | tSU:STO | 0.6 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Stop condition setup time (STANDARD-MODE) | tSU:STO | 4.7 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Bus release time before transfer start (FAST-MODE) | tBUF | 1.2 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Bus release time before transfer start (STANDARD-MODE) | tBUF | 4.7 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Internal write cycle time (FAST-MODE) | tWR | | | 5 | ms | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Internal write cycle time (STANDARD-MODE) | tWR | | | 5 | ms | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| Noise removal valid period, SDA and SCL terminal (FAST-MODE) | tI | | | 0.1 | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| Noise removal valid period, SDA and SCL terminal (STANDARD-MODE) | tI | | | 0.1 | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| WP hold time (FAST-MODE) | tHD:WP | 0 | | | ns | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| WP hold time (STANDARD-MODE) | tHD:WP | 0 | | | ns | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| WP setup time (FAST-MODE) | tSU:WP | 0.1 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| WP setup time (STANDARD-MODE) | tSU:WP | 0.1 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
| WP valid time (FAST-MODE) | tHIGH:WP | 1 | | | μs | FAST-MODE 2.5V≦Vcc≦5.5V | 3 |
| WP valid time (STANDARD-MODE) | tHIGH:WP | 1 | | | μs | STANDARD-MODE 1.8V≦Vcc≦5.5V | 3 |
## CAD (KiCad official)
- Symbol: `BR24L16FJ-WE2`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `br24l16fj-we2-etched.step` / `br24l16fj-we2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `br24l16fj-we2.step` / `br24l16fj-we2.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [ROHM Semicon datasheet](docs/br24l16fj-we2-datasheet.pdf) (39 pp, sha256 `7f7d69eca6c5c3aa`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/br24l16fj-we2-datasheet.pdf)