# BR24G128FJ-3GTE2

**ROHM Semicon** · EEPROM · SOIC-8

BR24G128FJ-3GTE2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Slave address setting input; must not be left open. |
| 2 | A1 | input | Slave address setting input; must not be left open. |
| 3 | A2 | input | Slave address setting input; must not be left open. |
| 4 | GND | power_in | Reference voltage for all inputs and outputs, 0 V. |
| 5 | SDA | bidirectional | Serial data input and output for the I2C bus. |
| 6 | SCL | input | Serial clock input for the I2C bus. |
| 7 | WP | input | Write protect terminal. |
| 8 | VCC | power_in | Connect the power source; operating supply range is 1.6 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | Vcc | -0.3 |  | 6.5 | V |  | 2 |
| Power Dissipation (SOP-J8) | Pd |  |  | 450 | mW | Derate by 4.5mW/°C when operating above Ta=25°C | 2 |
| Storage Temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| Operating Temperature | Topr | -40 |  | 85 | °C |  | 2 |
| Input Voltage / Output Voltage |  | -0.3 |  | 1 | V over Vcc (max) | Max not over 6.5V; min -1.0V when pulse width is 50ns or less | 2 |
| Junction Temperature | Tjmax |  |  | 150 | °C | Junction temperature at the storage condition | 2 |
| Electrostatic discharge voltage (human body model) | VESD | -4000 |  | 4000 | V | Human body model | 2 |
| Write Cycles |  | 1e+06 |  |  | Times | Ta=25°C, VCC=1.6V to 5.5V; Not 100% tested | 2 |
| Data Retention |  | 40 |  |  | Years | Ta=25°C, VCC=1.6V to 5.5V; Not 100% tested | 2 |
| Power Source Voltage | Vcc | 1.6 |  | 5.5 | V |  | 2 |
| Input Voltage | VIN | 0 |  |  | V | Maximum printed as Vcc | 2 |
| Input High Voltage1 | VIH1 | 0.7 |  | 1 | x VCC (min) / V over VCC (max) | 1.7V≤VCC≤5.5V | 2 |
| Input Low Voltage1 | VIL1 | -0.3 |  | 0.3 | V (min) / x VCC (max) | 1.7V≤VCC≤5.5V | 2 |
| Input High Voltage2 | VIH2 | 0.8 |  | 1 | x VCC (min) / V over VCC (max) | 1.6V≤VCC<1.7V | 2 |
| Input Low Voltage2 | VIL2 | -0.3 |  | 0.2 | V (min) / x VCC (max) | 1.6V≤VCC<1.7V | 2 |
| Output Low Voltage1 (SDA) | VOL1 |  |  | 0.4 | V | IOL=3.0mA, 2.5V≤Vcc≤5.5V (SDA) | 2 |
| Output Low Voltage2 (SDA) | VOL2 |  |  | 0.2 | V | IOL=0.7mA, 1.6V≤Vcc<2.5V (SDA) | 2 |
| Input Leakage Current | ILI | -1 |  | 1 | µA | VIN=0 to VCC | 2 |
| Output Leakage Current (SDA) | ILO | -1 |  | 1 | µA | VOUT=0 to VCC (SDA) | 2 |
| Supply Current (Write) | ICC1 |  |  | 2.5 | mA | VCC=5.5V, fSCL=400kHz, tWR=5ms, Byte write, Page write | 2 |
| Supply Current (Read) | ICC2 |  |  | 0.5 | mA | VCC=5.5V, fSCL=400kHz; Random read, current read, sequential read | 2 |
| Standby Current | ISB |  |  | 2 | µA | Vcc=5.5V, SDA・SCL=Vcc, A0,A1,A2=GND,WP=GND | 2 |
| Clock Frequency | fSCL |  |  | 400 | kHz |  | 3 |
| Data Clock High Period | tHIGH | 0.6 |  |  | µs |  | 3 |
| Data Clock Low Period | tLOW | 1.2 |  |  | µs |  | 3 |
| SDA, SCL (INPUT) Rise Time | tR |  |  | 1 | µs | Not 100% tested | 3 |
| SDA, SCL (INPUT) Fall Time | tF1 |  |  | 1 | µs | Not 100% tested | 3 |
| SDA (OUTPUT) Fall Time | tF2 |  |  | 0.3 | µs | Not 100% tested | 3 |
| Start Condition Hold Time | tHD:STA | 0.6 |  |  | µs |  | 3 |
| Start Condition Setup Time | tSU:STA | 0.6 |  |  | µs |  | 3 |
| Input Data Hold Time | tHD:DAT | 0 |  |  | ns |  | 3 |
| Input Data Setup Time | tSU:DAT | 100 |  |  | ns |  | 3 |
| Output Data Delay Time | tPD | 0.1 |  | 0.9 | µs |  | 3 |
| Output Data Hold Time | tDH | 0.1 |  |  | µs |  | 3 |
| Stop Condition Setup Time | tSU:STO | 0.6 |  |  | µs |  | 3 |
| Bus Free Time | tBUF | 1.2 |  |  | µs |  | 3 |
| Write Cycle Time | tWR |  |  | 5 | ms |  | 3 |
| Noise Spike Width (SDA and SCL) | tI |  |  | 0.1 | µs |  | 3 |
| WP Hold Time | tHD:WP | 1 |  |  | µs |  | 3 |
| WP Setup Time | tSU:WP | 0.1 |  |  | µs |  | 3 |
| WP High Period | tHIGH:WP | 1 |  |  | µs |  | 3 |

## CAD (KiCad official)

- Symbol: `BR24G128FJ-3GTE2`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `br24g128fj-3gte2-etched.step` / `br24g128fj-3gte2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `br24g128fj-3gte2.step` / `br24g128fj-3gte2.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ROHM Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588939100552638464) (38 pp, sha256 `01655ea5acba0135`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/br24g128fj-3gte2-datasheet.pdf)