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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	bq7791501pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	bq7791501pwr: viewers · Ray	1mo ago
bq7791501pwr-etched.fit.json	bq7791501pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq7791501pwr-etched.glb	bq7791501pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq7791501pwr-etched.step	bq7791501pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
bq7791501pwr.glb	Publish 0.1.0 · Ray	1mo ago
bq7791501pwr.kicad_mod	Publish 0.1.0 · Ray	1mo ago
bq7791501pwr.kicad_sym	Publish 0.1.0 · Ray	1mo ago
bq7791501pwr.lbr	Publish 0.1.0 · Ray	1mo ago
bq7791501pwr.step	Publish 0.1.0 · Ray	1mo ago
package.json	bq7791501pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
page.json	bq7791501pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
README.md	Initial commit: component/bq7791501pwr · Ray	1mo ago

BQ7791501PWR

Texas Instruments · Battery Management · TSSOP-24

BQ7791501PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Supply voltage input with operating range 3 V to 25 V and absolute maximum rating -0.3 V to 36 V.
2	AVDD	power_out	Analog supply voltage output with 1 µF capacitor connection and output voltage 2.1 V to 3.6 V.
3	VC5	input	Cell voltage sense input for highest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
4	VC4	input	Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
5	VC3	input	Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
6	VC2	input	Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
7	VC1	input	Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
8	VC0	input	Cell voltage sense input for lowest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V.
9	VSS	power_in	Analog ground reference connection for all analog circuits.
10	SRP	input	Current sense input connecting to battery side of sense resistor with input voltage -0.2 V to 0.8 V for discharge and charge current detection.
11	SRN	input	Current sense input connecting to pack side of sense resistor with input voltage -0.2 V to 0.8 V for overcurrent and short circuit detection.
12	DSG	output	Discharge FET driver output with voltage 0 V to 16 V to control low-side N-channel FET for discharge path.
13	CHG	output	Charge FET driver output with voltage 0 V to 16 V and absolute maximum -30 V to 20 V to control low-side N-channel FET for charge path.
14	LD	input	PACK- load removal detection input with input voltage 0 V to 16 V and absolute maximum -30 V to 20 V, clamped to 16 V to 20 V.
15	LPWR	output	HIBERNATE mode communication output with voltage 0 V to 3 V and absolute maximum -30 V to 3.6 V; connect to PRES of lower device in stacked configuration.
16	CBI	input	Cell balancing input; leave floating to disable or drive low to enable cell balancing with up to 50 mA current; input voltage 0 to AVDD.
17	OCDP	input	OCD1/2 fault detection delay programming input; connect resistor to VSS to program overcurrent detection delay; 10 MΩ resistor for upper devices in stack.
18	TS	input	Thermistor measurement input with voltage 0 to VTB for temperature-based protection; connect 10 kΩ resistor to VSS if not used.
19	VTB	output	Thermistor bias voltage output with output range 0 V to 3 V for thermistor measurement biasing.
20	CCFG	input	Cell in-series configuration input with voltage 0 to AVDD; <10% AVDD for 3-series, 65-100% for 4-series, floating for 5-series configuration.
21	CBO	output	Cell balancing output with voltage 0 to VDD; connect through 10 kΩ resistor to CBI of upper device in stacked configuration.
22	PRES	input	HIBERNATE mode input with voltage 0 V to 16 V; drive >1.25 V for NORMAL mode or leave floating for HIBERNATE mode with ultra-low power consumption.
23	CTRC	input	CHG FET control override input with voltage 0 to (VDD + 5) V; enable/disable CHG driver; use 10 MΩ current limit resistor.
24	CTRD	input	DSG FET control override input with voltage 0 to (VDD + 5) V; enable/disable DSG driver; use 10 MΩ current limit resistor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-24
Category	Power Management (PMIC)
Pins	24

CAD (KiCad official)

Symbol: BQ7791501PWR
Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
3D model: TSSOP-24 (KiCad packages3D, STEP)
3D model files: bq7791501pwr-etched.step / bq7791501pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7791501pwr.step / bq7791501pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (56 pp, sha256 0b1cab63aa1e53ef, retrieved 2026-09-24, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF