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BQ7791501PWR
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Texas Instruments Battery Management, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+61@@ -0,0 +1,61 @@+# BQ7791501PWR++**Texas Instruments** · Battery Management · TSSOP-24++BQ7791501PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD | power_in | Supply voltage input with operating range 3 V to 25 V and absolute maximum rating -0.3 V to 36 V. |+| 2 | AVDD | power_out | Analog supply voltage output with 1 µF capacitor connection and output voltage 2.1 V to 3.6 V. |+| 3 | VC5 | input | Cell voltage sense input for highest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 4 | VC4 | input | Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 5 | VC3 | input | Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 6 | VC2 | input | Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 7 | VC1 | input | Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 8 | VC0 | input | Cell voltage sense input for lowest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V. |+| 9 | VSS | power_in | Analog ground reference connection for all analog circuits. |+| 10 | SRP | input | Current sense input connecting to battery side of sense resistor with input voltage -0.2 V to 0.8 V for discharge and charge current detection. |+| 11 | SRN | input | Current sense input connecting to pack side of sense resistor with input voltage -0.2 V to 0.8 V for overcurrent and short circuit detection. |+| 12 | DSG | output | Discharge FET driver output with voltage 0 V to 16 V to control low-side N-channel FET for discharge path. |+| 13 | CHG | output | Charge FET driver output with voltage 0 V to 16 V and absolute maximum -30 V to 20 V to control low-side N-channel FET for charge path. |+| 14 | LD | input | PACK- load removal detection input with input voltage 0 V to 16 V and absolute maximum -30 V to 20 V, clamped to 16 V to 20 V. |+| 15 | LPWR | output | HIBERNATE mode communication output with voltage 0 V to 3 V and absolute maximum -30 V to 3.6 V; connect to PRES of lower device in stacked configuration. |+| 16 | CBI | input | Cell balancing input; leave floating to disable or drive low to enable cell balancing with up to 50 mA current; input voltage 0 to AVDD. |+| 17 | OCDP | input | OCD1/2 fault detection delay programming input; connect resistor to VSS to program overcurrent detection delay; 10 MΩ resistor for upper devices in stack. |+| 18 | TS | input | Thermistor measurement input with voltage 0 to VTB for temperature-based protection; connect 10 kΩ resistor to VSS if not used. |+| 19 | VTB | output | Thermistor bias voltage output with output range 0 V to 3 V for thermistor measurement biasing. |+| 20 | CCFG | input | Cell in-series configuration input with voltage 0 to AVDD; <10% AVDD for 3-series, 65-100% for 4-series, floating for 5-series configuration. |+| 21 | CBO | output | Cell balancing output with voltage 0 to VDD; connect through 10 kΩ resistor to CBI of upper device in stacked configuration. |+| 22 | PRES | input | HIBERNATE mode input with voltage 0 V to 16 V; drive >1.25 V for NORMAL mode or leave floating for HIBERNATE mode with ultra-low power consumption. |+| 23 | CTRC | input | CHG FET control override input with voltage 0 to (VDD + 5) V; enable/disable CHG driver; use 10 MΩ current limit resistor. |+| 24 | CTRD | input | DSG FET control override input with voltage 0 to (VDD + 5) V; enable/disable DSG driver; use 10 MΩ current limit resistor. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Power Management (PMIC) |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `BQ7791501PWR`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `bq7791501pwr-etched.step` / `bq7791501pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq7791501pwr.step` / `bq7791501pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq77915) (56 pp, sha256 `0b1cab63aa1e53ef`, retrieved 2026-09-24, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq7791501pwr-datasheet.pdf)
page.jsonadded+237@@ -0,0 +1,237 @@+{+ "slug": "bq7791501pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Battery Management, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "bq7791501pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "bq7791501pwr.kicad_sym",+ "bq7791501pwr.kicad_mod",+ "bq7791501pwr.glb",+ "bq7791501pwr.step",+ "bq7791501pwr.lbr",+ "docs/hero.png",+ "docs/bq7791501pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "BQ7791501PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-24",+ "pin_count": 24,+ "category": "Power Management (PMIC)",+ "subcategory": "Battery Management",+ "datasheet": "https://www.ti.com/cn/lit/gpn/bq77915",+ "parts": {+ "symbol": "bq7791501pwr.kicad_sym",+ "footprint": "bq7791501pwr.kicad_mod",+ "model_3d": "bq7791501pwr-etched.glb",+ "model_3d_plain": "bq7791501pwr.glb",+ "model_3d_step": "bq7791501pwr-etched.step",+ "model_3d_step_plain": "bq7791501pwr.step",+ "lbr": "bq7791501pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2876947"+ },+ "pins": [+ {+ "number": "1",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage input with operating range 3 V to 25 V and absolute maximum rating -0.3 V to 36 V."+ },+ {+ "number": "2",+ "name": "AVDD",+ "type": "power_out",+ "description": "Analog supply voltage output with 1 µF capacitor connection and output voltage 2.1 V to 3.6 V."+ },+ {+ "number": "3",+ "name": "VC5",+ "type": "input",+ "description": "Cell voltage sense input for highest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "4",+ "name": "VC4",+ "type": "input",+ "description": "Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "5",+ "name": "VC3",+ "type": "input",+ "description": "Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "6",+ "name": "VC2",+ "type": "input",+ "description": "Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "7",+ "name": "VC1",+ "type": "input",+ "description": "Cell voltage sense input with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "8",+ "name": "VC0",+ "type": "input",+ "description": "Cell voltage sense input for lowest cell with input voltage 0 V to 5 V and absolute maximum -0.3 V to 36 V."+ },+ {+ "number": "9",+ "name": "VSS",+ "type": "power_in",+ "description": "Analog ground reference connection for all analog circuits."+ },+ {+ "number": "10",+ "name": "SRP",+ "type": "input",+ "description": "Current sense input connecting to battery side of sense resistor with input voltage -0.2 V to 0.8 V for discharge and charge current detection."+ },+ {+ "number": "11",+ "name": "SRN",+ "type": "input",+ "description": "Current sense input connecting to pack side of sense resistor with input voltage -0.2 V to 0.8 V for overcurrent and short circuit detection."+ },+ {+ "number": "12",+ "name": "DSG",+ "type": "output",+ "description": "Discharge FET driver output with voltage 0 V to 16 V to control low-side N-channel FET for discharge path."+ },+ {+ "number": "13",+ "name": "CHG",+ "type": "output",+ "description": "Charge FET driver output with voltage 0 V to 16 V and absolute maximum -30 V to 20 V to control low-side N-channel FET for charge path."+ },+ {+ "number": "14",+ "name": "LD",+ "type": "input",+ "description": "PACK- load removal detection input with input voltage 0 V to 16 V and absolute maximum -30 V to 20 V, clamped to 16 V to 20 V."+ },+ {+ "number": "15",+ "name": "LPWR",+ "type": "output",+ "description": "HIBERNATE mode communication output with voltage 0 V to 3 V and absolute maximum -30 V to 3.6 V; connect to PRES of lower device in stacked configuration."+ },+ {+ "number": "16",+ "name": "CBI",+ "type": "input",+ "description": "Cell balancing input; leave floating to disable or drive low to enable cell balancing with up to 50 mA current; input voltage 0 to AVDD."+ },+ {+ "number": "17",+ "name": "OCDP",+ "type": "input",+ "description": "OCD1/2 fault detection delay programming input; connect resistor to VSS to program overcurrent detection delay; 10 MΩ resistor for upper devices in stack."+ },+ {+ "number": "18",+ "name": "TS",+ "type": "input",+ "description": "Thermistor measurement input with voltage 0 to VTB for temperature-based protection; connect 10 kΩ resistor to VSS if not used."+ },+ {+ "number": "19",+ "name": "VTB",+ "type": "output",+ "description": "Thermistor bias voltage output with output range 0 V to 3 V for thermistor measurement biasing."+ },+ {+ "number": "20",+ "name": "CCFG",+ "type": "input",+ "description": "Cell in-series configuration input with voltage 0 to AVDD; <10% AVDD for 3-series, 65-100% for 4-series, floating for 5-series configuration."+ },+ {+ "number": "21",+ "name": "CBO",+ "type": "output",+ "description": "Cell balancing output with voltage 0 to VDD; connect through 10 kΩ resistor to CBI of upper device in stacked configuration."+ },+ {+ "number": "22",+ "name": "PRES",+ "type": "input",+ "description": "HIBERNATE mode input with voltage 0 V to 16 V; drive >1.25 V for NORMAL mode or leave floating for HIBERNATE mode with ultra-low power consumption."+ },+ {+ "number": "23",+ "name": "CTRC",+ "type": "input",+ "description": "CHG FET control override input with voltage 0 to (VDD + 5) V; enable/disable CHG driver; use 10 MΩ current limit resistor."+ },+ {+ "number": "24",+ "name": "CTRD",+ "type": "input",+ "description": "DSG FET control override input with voltage 0 to (VDD + 5) V; enable/disable DSG driver; use 10 MΩ current limit resistor."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 56,+ "cost_usd": 0.5766,+ "at": "2026-09-24T10:56:06"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/bq77915",+ "pages": 56,+ "sha256": "0b1cab63aa1e53ef",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}