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BQ7791500PWT

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Texas Instruments Battery Management ICs, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BQ7791500PWT

Texas Instruments · Battery Management ICs · TSSOP-24

BQ7791500PWT from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Supply voltage input; recommended operating range 3 V to 25 V, absolute maximum 36 V.
2 AVDD power_out Analog supply output; connect only to a capacitor.
3 VC5 input Cell voltage sense input for the top cell; absolute maximum 36 V, and 0 to 5 V per cell relative to adjacent input.
4 VC4 input Cell voltage sense input; absolute maximum 36 V, and 0 to 5 V per cell relative to adjacent input.
5 VC3 input Cell voltage sense input; absolute maximum 36 V, and 0 to 5 V per cell relative to adjacent input.
6 VC2 input Cell voltage sense input; absolute maximum 36 V, and 0 to 5 V per cell relative to adjacent input.
7 VC1 input Cell voltage sense input; absolute maximum 36 V, and 0 to 5 V per cell relative to adjacent input.
8 VC0 input Cell voltage sense input for the bottom cell negative terminal; absolute maximum 3.6 V.
9 VSS power_in Analog ground.
10 SRP input Current sense input connecting to the battery side of the sense resistor; operating range -0.2 V to 0.8 V.
11 SRN input Current sense input connecting to the pack side of the sense resistor; operating range -0.2 V to 0.8 V.
12 DSG output DSG FET driver output; absolute maximum 20 V, operating output range 0 to 16 V.
13 CHG output CHG FET driver output; absolute range -30 V to 20 V, operating output range 0 to 16 V.
14 LD input PACK- load removal detection input; absolute range -30 V to 20 V, operating range 0 to 16 V.
15 LPWR output HIBERNATE mode communication pin; connect to the PRES pin of the lower device in a stack, or leave floating for a single device.
16 CBI input Cell balancing input; leave floating to disable balancing, drive low to enable, do not drive with an external supply, and in a stack connect to CBO of the immediate lower device.
17 OCDP input A resistor to VSS programs the OCD1/2 fault detection delay; use a 10-MΩ resistor to VSS for the upper devices in a stack.
18 TS input Thermistor measurement input; connect a 10-kΩ resistor to VSS if the function is not used.
19 VTB output Thermistor bias output; operating range 0 to 3 V.
20 CCFG input Cell in-series configuration input; operating range 0 to AVDD.
21 CBO output Cell balancing output; connect through a 10-kΩ resistor to CBI of the upper device in a stack, or leave floating for a single device.
22 PRES input HIBERNATE mode input; drive high for NORMAL mode, leave floating for HIBERNATE mode, and connect to LPWR of the upper device in a stack.
23 CTRC input CHG and DSG override input; operating range 0 to VDD+5 V, absolute maximum 36 V, with 10-MΩ current limit resistor recommended.
24 CTRD input CHG and DSG override input; operating range 0 to VDD+5 V, absolute maximum 36 V, with 10-MΩ current limit resistor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Power Supply Chip
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 3 25 V 5
Operating free-air temperature TOPR -40 85 °C 6
Cell input voltage range VI 0 5 V VC5-VC4 ... VC1-VC0 6
Absolute max VDD, VC5-VC1, CTRD, CTRC VI -0.3 36 V referenced to VSS 5
Absolute max LD VI -30 20 V referenced to VSS 5
Absolute max VC0, SRN, SRP, TS, AVDD, CCFG, CBI VI -0.3 3.6 V referenced to VSS 5
Absolute max DSG output VO -0.3 20 V 5
Absolute max CHG output VO -30 20 V 5
Absolute max cell balancing current IO 50 mA VC5..VC0 5
Storage temperature Tstg -65 150 °C 5
Lead temperature TSOLDER 300 °C soldering, 10 s 5
ESD HBM V(ESD) -1000 1000 V ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) -250 250 V JESD22-C101 5
Junction-to-ambient thermal resistance RΘJA 88.9 °C/W PW (TSSOP) 24 pins 7
Junction-to-case (top) thermal resistance RΘJC(top) 26.5 °C/W PW (TSSOP) 24 pins 7
Junction-to-board thermal resistance RΘJB 43.5 °C/W PW (TSSOP) 24 pins 7
Shutdown threshold VSHUT 2 3.25 V VDD falling, 6 to 0 V 7
AVDD voltage VAVDD 2.1 3.6 V CVDD = 1 µF 7
NORMAL mode current ICC 8 15 µA Cell1 through Cell5 = 4 V, VDD = 20 V, No cell balancing 7
NORMAL mode current, balancing ICC 48 80 µA Cell balancing cells 3, 4 or 5 7
HIBERNATE mode current IHIB 2 3 µA Cell1 through Cell5 = 4 V, VDD = 20 V, HIBERNATE mode 7
Fault condition current ICFAULT 10 15 µA State comparator on 7
SHUTDOWN mode current IOFF 0.5 µA VDD < VSHUT, CTRC/CTRD floating 7
Input leakage current at VCx pins ILKG_OW_DIS -100 0 100 nA All cell voltages = 4 V, open-wire disable configuration 7
Open-wire sink current at VCx pins ILKG_100nA 30 110 175 nA All cell voltages = 4 V, 100-nA configuration 7
OV detection accuracy VVA -10 10 mV TA = 25°C, OV detection accuracy 8
UV detection accuracy VVA -18 18 mV TA = 25°C, UV detection accuracy 8
OV/UV detection accuracy 0 to 60°C VVA -28 26 mV TA = 0 to 60°C 8
OV/UV detection accuracy full temp VVA -40 40 mV TA = -40 to +85°C 8
Overtemperature in discharge threshold 65°C VOTD 19.69 20.56 21.86 %VTB Threshold for 65°C based on a 10k pullup and 103AT thermistor 8
Overtemperature in discharge recovery 55°C VOTD_REC 25.18 26.12 27.44 %VTB Recovery threshold at 55°C for when VOTD is at 65°C 8
Overtemperature in charge threshold 45°C VOTC 32.14 32.94 34.54 %VTB Threshold for 45°C based on a 10k pullup and 103AT thermistor 8
Overtemperature in charge recovery 35°C VOTC_REC 38.63 40.97 40.99 %VTB Recovery threshold at 35°C for when VOTD is at 45°C 8
Undertemperature in discharge threshold -10°C VUTD 80.04 80.94 83.1 %VTB Threshold for -10°C based on a 10k pullup and 103AT thermistor 8
Undertemperature in discharge recovery 0°C VUTD_REC 71.7 73.18 74.86 %VTB Recovery threshold at 0°C for when VUTD is at -10°C 8
Undertemperature in charge threshold 0°C VUTC 71.7 73.18 74.86 %VTB Threshold for 0°C based on a 10k pullup and 103AT thermistor 8
Undertemperature in charge recovery 10°C VUTC_REC 64.67 65.52 67.46 %VTB Recovery threshold at 10°C for when VUTC is at 0°C 8
OCD1 detection accuracy at lower thresholds VCCAL -30 30 % VOCD1 ≤ 20 mV 9
OCC, OCD1, OCD2, SCD detection accuracy VCCAH -20 20 % VOCD1 > 20 mV; all OCC, OCD2 and SCD threshold ranges 9
Open-wire fault voltage threshold VOW 450 500 550 mV Voltage falling on VCx, 3.6 V to 0 V 9
Overvoltage detection delay, 1-s option tOVn_DELAY 0.8 1 1.4 s 1-s delay option 9
Undervoltage detection delay, 1-s option tUVn_DELAY 0.8 1 1.5 s 1-s delay option 9
Open-wire detection delay time tOWn_DELAY 3.6 4.5 5.3 s 9
Overtemperature charge detection delay tOTC_DELAY 3.6 4.5 5.3 s 9
Overtemperature discharge detection delay tOTD_DELAY 3.6 4.5 5.3 s 9
Overcurrent discharge 1 delay, 180-ms option tOCD1_DELAY 155 180 205 ms 180-ms delay option 9
Overcurrent discharge 2 delay, 180-ms option tOCD2_DELAY 155 180 205 ms 180-ms delay option 10
Short-circuit detection delay, 960-µs option tSCD_DELAY 528 960 1450 µs 960-µs delay option 10
Overcurrent charge detection delay tOCC_DELAY 8 10 12 ms 10
CHG/DSG on voltage, VDD ≥ 12 V VFETON 11 12 14 V VDD ≥ 12 V, CL = 10 nF 10
CHG/DSG off voltage VFETOFF 0.5 V 1-mA resistive load, CHG clamped to ground when CHG/DSG is off. 10
CHG on rise time tCHGON 50 150 µs CL = 10 nF, 10% to 90% 10
DSG on rise time tDSGON 2 75 µs CL = 10 nF, 10% to 90% 10
CHG off resistance RCHGOFF 0.3 0.5 0.75 kΩ CHG off and pin held at 2V 10
DSG off resistance RDSGOFF 10 16 Ω DSG off and pin held at 100 mV 10
Cell balancing internal FET resistance RBAL 8 12 20 Ω Cell1 through Cell5 = 4 V, VDD = 20 V 10
PRES high threshold VPRESH 1.25 1.5 1.75 V 10
LD threshold VLDT 1.25 1.3 1.35 V OPEN pack terminals 11
LD clamp voltage VLDCLAMP 16 19 20 V ILDCLAMP = 300 µA 11
Overvoltage threshold (BQ7791500) VOV 4200 mV BQ7791500 option, 1 s delay, 200 mV hysteresis 3
Undervoltage threshold (BQ7791500) VUV 2900 mV BQ7791500 option, 1 s delay, 400 mV hysteresis 3
OCD1 threshold (BQ7791500) VOCD1 60 mV BQ7791500 option, 180 ms delay (printed without sign) 3
SCD threshold (BQ7791500) VSCD 120 mV BQ7791500 option, 0.96 ms delay (printed without sign) 3

CAD (KiCad official)

  • Symbol: BQ7791500PWT
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: bq7791500pwt-etched.step / bq7791500pwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7791500pwt.step / bq7791500pwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 a4d8b11fe0446f32, retrieved 2026-10-27, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF