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BQ7695204PFBR

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Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs bq7695204pfbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers bq7695204pfbr: viewers · Ray
bq7695204pfbr-etched.fit.json bq7695204pfbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
bq7695204pfbr-etched.glb bq7695204pfbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
bq7695204pfbr-etched.step bq7695204pfbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
bq7695204pfbr.glb Publish 0.1.0 · Ray
bq7695204pfbr.kicad_mod Publish 0.1.0 · Ray
bq7695204pfbr.kicad_sym Publish 0.1.0 · Ray
bq7695204pfbr.lbr Publish 0.1.0 · Ray
bq7695204pfbr.step Publish 0.1.0 · Ray
package.json bq7695204pfbr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json bq7695204pfbr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md Initial commit: component/bq7695204pfbr · Ray

BQ7695204PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7695204PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VC15 input Fifteenth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC14-0.3 to VSS+85 V.
2 VC14 input Fourteenth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC13-0.3 to VSS+85 V.
3 VC13 input Thirteenth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC12-0.3 to VSS+85 V.
4 VC12 input Twelfth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC11-0.3 to VSS+85 V.
5 VC11 input Eleventh cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC10-0.3 to VSS+85 V.
6 VC10 input Tenth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC9-0.3 to VSS+85 V.
7 VC9 input Ninth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC8-0.3 to VSS+85 V.
8 VC8 input Eighth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC7-0.3 to VSS+85 V.
9 VC7 input Seventh cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC6-0.3 to VSS+85 V.
10 VC6 input Sixth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC5-0.3 to VSS+85 V.
11 VC5 input Fifth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC4-0.3 to VSS+85 V.
12 VC4 input Fourth cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC3-0.3 to VSS+85 V.
13 VC3 input Third cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC2-0.3 to VSS+85 V.
14 VC2 input Second cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC1-0.3 to VSS+85 V.
15 VC1 input First cell voltage sense input pin with balance current path and operating voltage range maximum of VSS-0.3 V and VC0-0.3 to VSS+85 V.
16 VC0 input Negative terminal sense voltage input of first cell with balance current return path and operating voltage range VSS-0.3 V to VSS+6 V.
17 VSS power_in Device ground reference terminal.
18 SRP input Sense resistor positive input to coulomb counter for current measurement with operating range -0.2 V to 0.2 V.
19 NC unconnected Not connected to silicon.
20 SRN input Sense resistor negative input to coulomb counter for current measurement with operating range -0.2 V to 0.2 V.
21 TS1 input Thermistor temperature input or general purpose ADC input with operating voltage range 0 V to VREG18+0.3 V.
22 TS2 input Thermistor temperature input with wakeup function from SHUTDOWN mode or general purpose ADC input with operating voltage range 0 V to VREG18 V.
23 TS3 input Thermistor temperature input or general purpose ADC input with operating voltage range 0 V to VREG18+0.3 V.
24 REG18 power_out Internal 1.8 V regulated LDO output for internal use only with output voltage range VSS-0.3 V to VSS+2 V.
25 ALERT bidirectional Multifunction pin for alarm interrupt output or HDQ interface or thermistor input or ADC measurement with voltage range VSS-0.3 V to VSS+6 V.
26 SCL bidirectional I2C serial clock or SPI clock multifunction open-drain pin with voltage range VSS-0.3 V to VSS+6 V.
27 SDA bidirectional I2C serial data or SPI MISO multifunction open-drain pin with voltage range VSS-0.3 V to VSS+6 V.
28 HDQ bidirectional HDQ interface or SPI MOSI or thermistor or ADC input multifunction pin with voltage range VSS-0.3 V to VSS+6 V.
29 CFETOFF bidirectional Charge FET disable input or SPI chip select or thermistor or ADC input multifunction pin with voltage range VSS-0.3 V to VSS+6 V.
30 DFETOFF bidirectional Discharge FET disable or BOTHOFF input or thermistor or ADC input multifunction pin with voltage range VSS-0.3 V to VSS+6 V.
31 DCHG output Charge FET fault status open-drain output or thermistor or ADC input multifunction pin with output voltage range VSS-0.3 V to VSS+6 V.
32 DDSG output Discharge FET fault status open-drain output or thermistor or ADC input multifunction pin with output voltage range VSS-0.3 V to VSS+6 V.
33 RST_SHUT input Reset or shutdown digital input pin with operating voltage range VSS-0.3 V to VSS+6 V.
34 REG2 power_out Programmable LDO output configurable for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V with output voltage range VSS-0.3 V to minimum of VSS+6 or VREGIN+0.3 V.
35 REG1 power_out Programmable LDO output configurable for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V with output voltage range VSS-0.3 V to minimum of VSS+6 or VREGIN+0.3 V.
36 REGIN input Pre-regulator input for REG1 and REG2 LDOs with operating voltage range maximum of VSS-0.3 or VBREG-5.5 to minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 V.
37 BREG output Base control signal for external preregulator BJT open-drain output with voltage range maximum of VSS-0.3 or VREGIN-0.3 to VREGIN+5.5 V.
38 FUSE bidirectional Fuse sense and drive multifunction pin for secondary protection with operating voltage range VSS-0.3 V to minimum of VSS+20 or VBAT+0.3 V.
39 PDSG output Predischarge PFET gate drive open-drain output with maximum voltage range maximum of VBAT-10 or VLD-10 to VSS+85 V.
40 PCHG output Precharge PFET gate drive open-drain output with maximum voltage range maximum of VBAT-10 or VLD-10 to VSS+85 V.
41 LD bidirectional Load detect input and output pin with operating voltage range 0 V to 80 V.
42 PACK input Pack sense input pin for pack voltage measurement and overcurrent protection with operating voltage range 0 V to 80 V.
43 DSG output NMOS discharge FET gate drive open-drain output with maximum voltage range VSS-0.3 V to VSS+85 V.
44 NC unconnected Not connected to silicon.
45 CHG output NMOS charge FET gate drive open-drain output with maximum voltage range VSS-0.3 V to VSS+85 V.
46 CP1 bidirectional Charge pump capacitor pin with operating voltage range VBAT-0.3 V to minimum of VSS+85 or VBAT+15 V.
47 BAT power_in Primary power supply input from battery stack with operating voltage range VSS-0.3 V to VSS+85 V.
48 VC16 input Sixteenth cell voltage sense input and top-of-stack measurement point with maximum voltage range maximum of VSS-0.3 and VC15-0.3 to VSS+85 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ7695204PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq7695204pfbr-etched.step / bq7695204pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7695204pfbr.step / bq7695204pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (88 pp, sha256 0a51de7a50876154, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF