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BQ7695202PFBR

Texas Instruments · Battery Management ICs · TQFP-48(7x7)

BQ7695202PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VC15	input	Sense voltage input for the fifteenth cell from the bottom of the stack, balance current input for that cell, and return balance current for the sixteenth cell.
2	VC14	input	Sense voltage input for the fourteenth cell from the bottom of the stack, balance current input for that cell, and return balance current for the fifteenth cell.
3	VC13	input	Sense voltage input for the thirteenth cell from the bottom of the stack, balance current input for that cell, and return balance current for the fourteenth cell.
4	VC12	input	Sense voltage input for the twelfth cell from the bottom of the stack, balance current input for that cell, and return balance current for the thirteenth cell.
5	VC11	input	Sense voltage input for the eleventh cell from the bottom of the stack, balance current input for that cell, and return balance current for the twelfth cell.
6	VC10	input	Sense voltage input for the tenth cell from the bottom of the stack, balance current input for that cell, and return balance current for the eleventh cell.
7	VC9	input	Sense voltage input for the ninth cell from the bottom of the stack, balance current input for that cell, and return balance current for the tenth cell.
8	VC8	input	Sense voltage input for the eighth cell from the bottom of the stack, balance current input for that cell, and return balance current for the ninth cell.
9	VC7	input	Sense voltage input for the seventh cell from the bottom of the stack, balance current input for that cell, and return balance current for the eighth cell.
10	VC6	input	Sense voltage input for the sixth cell from the bottom of the stack, balance current input for that cell, and return balance current for the seventh cell.
11	VC5	input	Sense voltage input for the fifth cell from the bottom of the stack, balance current input for that cell, and return balance current for the sixth cell.
12	VC4	input	Sense voltage input for the fourth cell from the bottom of the stack, balance current input for that cell, and return balance current for the fifth cell.
13	VC3	input	Sense voltage input for the third cell from the bottom of the stack, balance current input for that cell, and return balance current for the fourth cell.
14	VC2	input	Sense voltage input for the second cell from the bottom of the stack, balance current input for that cell, and return balance current for the third cell.
15	VC1	input	Sense voltage input for the first cell from the bottom of the stack, balance current input for that cell, and return balance current for the second cell.
16	VC0	input	Sense voltage input for the negative terminal of the first cell from the bottom of the stack and return balance current for the first cell.
17	VSS	power_in	Device ground.
18	SRP	input	Coulomb counter analog input at the top of the sense resistor, where charging current produces a positive voltage at SRP relative to SRN.
19	NC	unconnected	Not connected to silicon; can be left floating or connected to an adjacent pin or VSS.
20	SRN	input	Coulomb counter analog input at the bottom of the sense resistor, where charging current produces a positive voltage at SRP relative to SRN.
21	TS1	bidirectional	Thermistor input or general purpose ADC input.
22	TS2	bidirectional	Thermistor input that also functions as wakeup from SHUTDOWN, or general purpose ADC input.
23	TS3	bidirectional	Thermistor input or general purpose ADC input.
24	REG18	power_out	Internal 1.8-V LDO output, for internal use only, requiring a 2.2 µF typical external capacitor to VSS.
25	ALERT	bidirectional	Multifunction pin that can be ALERT output, HDQ I/O, thermistor input, general purpose ADC input, or general purpose digital output.
26	SCL	bidirectional	Multifunction open-drain pin that can be I2C SCL or SPI_SCLK.
27	SDA	bidirectional	Multifunction open-drain pin that can be I2C SDA or SPI_MISO.
28	HDQ	bidirectional	Multifunction pin that can be HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output.
29	CFETOFF	bidirectional	Multifunction pin that can be CFETOFF, SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output.
30	DFETOFF	bidirectional	Multifunction pin that can be DFETOFF, BOTHOFF, thermistor input, general purpose ADC input, or general purpose digital output.
31	DCHG	bidirectional	Multifunction pin that can be DCHG, thermistor input, general purpose ADC input, or general purpose digital output.
32	DDSG	bidirectional	Multifunction pin that can be DDSG, thermistor input, general purpose ADC input, or general purpose digital output.
33	RST_SHUT	input	Digital input for reset or shutdown; high resets the digital logic and high for 1 second enters SHUTDOWN, otherwise driven low.
34	REG2	power_out	Second LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
35	REG1	power_out	First LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
36	REGIN	power_in	Input pin for the REG1 and REG2 LDOs, supplied from the REG0 preregulator or an external source.
37	BREG	output	Base control signal for the external preregulator transistor.
38	FUSE	bidirectional	Fuse sense and drive pin.
39	PDSG	output	Predischarge PFET control output.
40	PCHG	output	Precharge PFET control output.
41	LD	bidirectional	Load detect pin.
42	PACK	input	Pack sense input pin.
43	DSG	output	NMOS discharge FET drive output pin.
44	NC	unconnected	Not connected to silicon; can be left floating or connected to an adjacent pin or VSS.
45	CHG	output	NMOS charge FET drive output pin.
46	CP1	passive	Charge pump capacitor pin; connect to BAT (pin 47) if not used.
47	BAT	power_in	Primary power supply input pin.
48	VC16	input	Sense voltage input for the sixteenth cell from the bottom of the stack, balance current input for that cell, and top-of-stack measurement point.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	Power Management ICs
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range BAT (absolute max)	VBAT			85	V	BAT, relative to VSS (VSS+85); min VSS-0.3	7
Input voltage range PACK, LD	VIN			85	V	VSS+85; min VSS-0.3	7
Input voltage range VC0	VIN			6	V	VSS+6; min VSS-0.3	8
Output voltage range CHG	VO			85	V	VSS+85; min VSS-0.3	8
Output voltage range DSG	VO			85	V	VSS+85; min VSS-0.3	8
Output voltage range REG18	VO			2	V	VSS+2; min VSS-0.3	8
Maximum cell balancing current through a single cell				100	mA	VC0, VC16	8
Maximum VSS current	ISS			75	mA		8
Functional temperature	TFUNC	-40		85	°C		8
Junction temperature	TJ	-55		150	°C		8
Storage temperature	TSTG	-55		150	°C		8
ESD HBM	V(ESD)	-1000		1000	V	Human body model, ANSI/ESDA/JEDEC JS-001, all pins	8
ESD CDM	V(ESD)	-250		250	V	Charged device model, ANSI/ESDA/JEDEC JS-002, all pins	9
Supply voltage (normal operation)	VBAT	4.7		80	V	Voltage on BAT pin (normal operation)	9
Supply voltage (OTP programming)	VBAT	10		12	V	Voltage on BAT pin (OTP programming)	9
OTP programming temperature	TOTP	-40		45	°C		9
Power-on reset rising threshold	VPORA	3		4	V	Rising threshold on BAT	9
Power-on reset hysteresis	VPORA_HYS		180		mV	Device shuts down when BAT < VPORA - VPORA_HYS	9
Wake on LD voltage	VWAKEONLD	0.8	1.45	2.25	V	Rising edge on LD, with BAT already in valid range	9
Wake on TS2 voltage	VWAKEONTS2	0.7		1.1	V	Falling edge on TS2, with BAT already in valid range	9
Input voltage range PACK, LD	VIN	0		80	V	PACK, LD	9
Input voltage range digital pins	VIN	0		5.5	V	REG1, REG2, RST_SHUT, ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, except when used for ADC input or thermistor	9
Input voltage range TS pins as ADC/thermistor	VIN	0			V	Max is VREG18; TS1, TS2, TS3 etc. configured for ADC input or thermistor	9
Input voltage range SRP, SRN, SRP-SRN	VIN	-0.2		0.2	V	while measuring current	9
Input voltage range SRP, SRN	VIN	-0.2		0.75	V	without measuring current	9
Input voltage range VVC(0)	VIN	-0.2		0.5	V		9
External cell input resistance	RC	20		100	Ω		9
External cell input capacitance	CC	0.1	0.22	1	µF		10
Output voltage range LD	VO			80	V	LD	10
Output voltage range CHG, DSG, CP1	VO			85	V	CHG, DSG, CP1	10
Operating temperature	TOPR	-40		85	°C		10
Cell voltage measurement accuracy	VCELL(ACC)	-5		5	mV	2 V < VVC(x) - VVC(x-1) < 5 V, TA = 25°C, 1 ≤ x ≤ 16	10
Cell voltage measurement accuracy	VCELL(ACC)	-10		10	mV	2 V < VVC(x) - VVC(x-1) < 5 V, TA = 0°C to 60°C, 1 ≤ x ≤ 16	10
Cell voltage measurement accuracy	VCELL(ACC)	-15		15	mV	-0.2 V < VVC(x) - VVC(x-1) < 5.5 V, TA = -40°C to 85°C, 1 ≤ x ≤ 16	10
Stack voltage measurement accuracy	VSTACK(ACC)	-0.5		0.5	V	0 V < VVC16 - VVSS < 80 V, TA = -40°C to 85°C	10
PACK pin voltage measurement accuracy	VPACK(ACC)	-0.5		0.5	V	0 V < VPACK < 80 V, TA = -40°C to 85°C	10
LD pin voltage measurement accuracy	VLD(ACC)	-0.5		0.5	V	0 V < VLD < 80 V, TA = -40°C to 85°C	10
Junction-to-ambient thermal resistance	RθJA		66		°C/W	PFB (TQFP) 48 pins	10
Junction-to-case (top) thermal resistance	RθJC(top)		19.6		°C/W		10
Junction-to-board thermal resistance	RθJB		29.3		°C/W		10
Junction-to-top characterization parameter	ΨJT		0.8		°C/W		10
Junction-to-board characterization parameter	ΨJB		29.1		°C/W		10
Normal mode current	INORMAL		286		µA	Regular measurements and protections active, REG1 = 3.3 V with no load, REG2 = OFF, CHG = ON in 11V overdrive mode, DSG = ON in 11V overdrive mode, FASTADC = 0, no communication	10
SLEEP mode current	ISLEEP_1		41		µA	REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = ON in 11V overdrive mode, no communication, Sleep Voltage Time = 5 s	11
SLEEP mode current	ISLEEP_2		24		µA	REG1 = OFF, REG2 = OFF, CHG = OFF, DSG = source follower mode, no communication, Sleep Voltage Time = 5 s	11
DEEPSLEEP mode current	IDEEPSLEEP_1		10.7		µA	REG1 = 3.3 V with no load, REG2 = OFF, LFO = ON, no communication	11
DEEPSLEEP mode current	IDEEPSLEEP_2		9.2		µA	REG1 = 3.3 V with no load, REG2 = OFF, LFO = OFF, no communication	11
SHUTDOWN mode current	ISHUTDOWN		1	3.1	µA	All blocks powered down except TS2 wakeup circuit, no communication	11
Internal cell balancing resistance	R(CB)	15	28	46	Ω	RDS(ON) at VVC(n) - VVC(n-1) = 1.5V, 1 ≤ n ≤ 16, VBAT ≥ 4.7 V	18
Internal cell open wire check current	I(OW)	22	54	95	µA	VCx > VSS + 0.8 V, 1 ≤ x ≤ 4; VCx > VSS + 2.8 V, 5 ≤ x ≤ 16	18
Internal pullup resistance 18 kΩ	R(TS_PU)	14.4	18.3	21.6	kΩ	Setting for nominal 18-kΩ	19
Internal pullup resistance 180 kΩ	R(TS_PU)	140	178	216	kΩ	Setting for nominal 180-kΩ	19
HFO frequency error	fHFO(ERR)	-4	0.25	4	%	TA = -40°C to +85°C, includes frequency drift	19
LFO frequency error	fLFO(ERR)	-1.5	0.25	1.5	%	Full-speed setting, TA = -10°C to +60°C, includes frequency drift	19
LFO frequency error	fLFO(ERR)	-2.5	0.25	2.5	%	Full-speed setting, TA = -40°C to +85°C, includes frequency drift	19
ADC integral nonlinearity	B(ADC_INL)	-6.6		6.6	LSB	16-bit, best fit over -0.1 V to 5.5 V	17
ADC integral nonlinearity	B(ADC_INL)	-4		4	LSB	16-bit, best fit over -0.2 V to 0.2 V	17
Differential cell offset error	B(ADC_OFF_CELL)	-2.75		3.5	LSB	16-bit, uncalibrated, using VC16 - VC15	17
ADC gain	B(ADC_GAIN)	5385	5406	5427	LSB/V	16-bit, differential cell input mode on VC16-VC15, uncalibrated	17
ADC gain drift	B(ADC_GAIN_DRIFT)	-0.25	0.025	0.25	LSB/V/°C	Change in gain over operating temperature range vs 30°C	17

CAD (KiCad official)

Symbol: BQ7695202PFBR
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: bq7695202pfbr-etched.step / bq7695202pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7695202pfbr.step / bq7695202pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (87 pp, sha256 a9d512dfdac12910, retrieved 2026-10-22, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF