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BQ7695201PFBR

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Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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BQ7695201PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7695201PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VC15 input Sense voltage input pin for the fifteenth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
2 VC14 input Sense voltage input pin for the fourteenth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
3 VC13 input Sense voltage input pin for the thirteenth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
4 VC12 input Sense voltage input pin for the twelfth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
5 VC11 input Sense voltage input pin for the eleventh cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
6 VC10 input Sense voltage input pin for the tenth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
7 VC9 input Sense voltage input pin for the ninth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
8 VC8 input Sense voltage input pin for the eighth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
9 VC7 input Sense voltage input pin for the seventh cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
10 VC6 input Sense voltage input pin for the sixth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
11 VC5 input Sense voltage input pin for the fifth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
12 VC4 input Sense voltage input pin for the fourth cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
13 VC3 input Sense voltage input pin for the third cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
14 VC2 input Sense voltage input pin for the second cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
15 VC1 input Sense voltage input pin for the first cell from the bottom of the stack, with 2.0V to 5.5V input range recommended.
16 VC0 input Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack, with -0.2V to 0.5V input range recommended.
17 VSS power_in Device ground reference point.
18 SRP input Analog input pin connected to the internal coulomb counter for integrating voltage between SRP and SRN, with ±0.2V input range recommended.
19 NC unconnected This pin is not connected to silicon.
20 SRN input Analog input pin connected to the internal coulomb counter for integrating voltage between SRP and SRN, with ±0.2V input range recommended.
21 TS1 tri_state Multifunction pin with open-drain capability; can function as thermistor input or general-purpose ADC input, with 0 to VREG18 voltage range.
22 TS2 tri_state Multifunction pin with open-drain capability; can function as thermistor input, wakeup from SHUTDOWN, or general-purpose ADC input, with 0 to VREG18 voltage range.
23 TS3 tri_state Multifunction pin with open-drain capability; can function as thermistor input or general-purpose ADC input, with 0 to VREG18 voltage range.
24 REG18 power_out Internal 1.8-V LDO output for internal use only, regulated voltage with ±1.5% line regulation.
25 ALERT tri_state Multifunction pin with open-drain capability; can function as ALERT output, HDQ I/O, thermistor input, ADC input, or digital output, with 0 to 5.5V input range.
26 SCL tri_state Multifunction I2C or SPI open-drain pin; can function as SCL or SPI_SCLK, with 0 to 5.5V input range.
27 SDA tri_state Multifunction I2C or SPI open-drain pin; can function as SDA or SPI_MISO, with 0 to 5.5V input range.
28 HDQ tri_state Multifunction pin with open-drain capability; can function as HDQ I/O, SPI_MOSI, thermistor input, ADC input, or digital output, with 0 to VREG18 input range.
29 CFETOFF tri_state Multifunction pin with open-drain capability; can function as CHG FET disable, SPI_CS, thermistor input, ADC input, or digital output, with 0 to VREG18 input range.
30 DFETOFF tri_state Multifunction pin with open-drain capability; can function as DSG FET disable, BOTHOFF, thermistor input, ADC input, or digital output, with 0 to VREG18 input range.
31 DCHG tri_state Multifunction open-drain pin; can function as CHG fault indicator, thermistor input, ADC input, or digital output, with 0 to VREG18 input range.
32 DDSG tri_state Multifunction open-drain pin; can function as DSG fault indicator, thermistor input, ADC input, or digital output, with 0 to VREG18 input range.
33 RST_SHUT input Digital input pin for device reset or SHUTDOWN mode control, with 0 to 5.5V input range.
34 REG2 power_out Second programmable LDO output, configurable to 1.8V, 2.5V, 3.0V, 3.3V, or 5.0V with up to 45mA output current.
35 REG1 power_out First programmable LDO output, configurable to 1.8V, 2.5V, 3.0V, 3.3V, or 5.0V with up to 45mA output current.
36 REGIN input Input pin for REG1 and REG2 LDO regulators, typically supplied with approximately 5.5V.
37 BREG output Analog output pin providing base control signal for external preregulator transistor, with 2.5mA maximum short-circuit current.
38 FUSE bidirectional Analog bidirectional pin for chemical fuse drive and secondary protector sensing, with VSS-0.3V to minimum(VSS+20V, VBAT+0.3V) range.
39 PDSG output Analog output pin for predischarge PFET control, sourcing current with 30µA typical pulldown capability.
40 PCHG output Analog output pin for precharge PFET control, sourcing current with 30µA typical pulldown capability.
41 LD bidirectional Load detect bidirectional pin for autonomous load removal detection, with 0 to 80V output range and 35-172µA internal pullup.
42 PACK input Pack voltage sense input pin for main pack terminal measurement, with 0 to 80V input range and ±0.5V accuracy.
43 DSG output NMOS discharge FET gate drive output, providing high-side gate drive signal with VSS-0.3V to VSS+85V output range.
44 NC unconnected This pin is not connected to silicon.
45 CHG output NMOS charge FET gate drive output, providing high-side gate drive signal with VSS-0.3V to VSS+85V output range.
46 CP1 bidirectional Charge pump capacitor connection point for generating NFET gate overdrive voltage, with VSS-0.3V to minimum(VSS+85V, VBAT+15V) range.
47 BAT power_in Primary power supply input from battery pack, with 4.7V to 80V operating range and internal 1.8V regulated supply generation.
48 VC16 input Sense voltage input pin for the sixteenth cell from the bottom of the stack and top-of-stack measurement point, with 2.0V to 5.5V input range recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ7695201PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq7695201pfbr-etched.step / bq7695201pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7695201pfbr.step / bq7695201pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (88 pp, sha256 0a51de7a50876154, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF