component
BQ7694202PFBR
Public Made by Adomby adom
Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# BQ7694202PFBR++**Texas Instruments** · Battery Management · TQFP-48(7x7)++BQ7694202PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | This pin is not connected to silicon. |+| 2 | VC9 | input | Sense voltage input and balance current input for the ninth cell from the bottom of the stack. |+| 3 | NC | unconnected | This pin is not connected to silicon. |+| 4 | VC8 | input | Sense voltage input and balance current input for the eighth cell from the bottom of the stack. |+| 5 | NC | unconnected | This pin is not connected to silicon. |+| 6 | VC7 | input | Sense voltage input and balance current input for the seventh cell from the bottom of the stack. |+| 7 | NC | unconnected | This pin is not connected to silicon. |+| 8 | VC6 | input | Sense voltage input and balance current input for the sixth cell from the bottom of the stack. |+| 9 | NC | unconnected | This pin is not connected to silicon. |+| 10 | VC5 | input | Sense voltage input and balance current input for the fifth cell from the bottom of the stack. |+| 11 | NC | unconnected | This pin is not connected to silicon. |+| 12 | VC4 | input | Sense voltage input and balance current input for the fourth cell from the bottom of the stack. |+| 13 | VC3 | input | Sense voltage input and balance current input for the third cell from the bottom of the stack. |+| 14 | VC2 | input | Sense voltage input and balance current input for the second cell from the bottom of the stack. |+| 15 | VC1 | input | Sense voltage input and balance current input for the first cell from the bottom of the stack. |+| 16 | VC0 | input | Sense voltage input for negative terminal of the first cell and return balance current. |+| 17 | VSS | power_in | Device ground. |+| 18 | SRP | input | Analog input to coulomb counter for integrating differential voltage across sense resistor, positive terminal. |+| 19 | NC | unconnected | This pin is not connected to silicon. |+| 20 | SRN | input | Analog input to coulomb counter for integrating differential voltage across sense resistor, negative terminal. |+| 21 | TS1 | bidirectional | Thermistor input or general purpose ADC/digital output pin. |+| 22 | TS2 | bidirectional | Thermistor input with wakeup from SHUTDOWN capability or general purpose ADC/digital output pin. |+| 23 | TS3 | bidirectional | Thermistor input or general purpose ADC/digital output pin. |+| 24 | REG18 | power_out | Internal 1.8 V LDO output for internal device use only. |+| 25 | ALERT | bidirectional | Multifunction pin for ALERT output, HDQ interface, thermistor input, ADC input, or digital output. |+| 26 | SCL | bidirectional | I2C clock or SPI clock interface pin. |+| 27 | SDA | bidirectional | I2C data or SPI MISO interface pin. |+| 28 | HDQ | bidirectional | HDQ single-wire, SPI MOSI interface, or multifunction ADC/digital pin. |+| 29 | CFETOFF | bidirectional | Charge FET control, SPI chip select, or multifunction ADC/digital pin. |+| 30 | DFETOFF | bidirectional | Discharge FET control, BOTHOFF, or multifunction ADC/digital pin. |+| 31 | DCHG | bidirectional | Charge FET fault signal output or general purpose ADC/digital output pin. |+| 32 | DDSG | bidirectional | Discharge FET fault signal output or general purpose ADC/digital output pin. |+| 33 | RST_SHUT | input | Digital input pin for device reset or shutdown control. |+| 34 | REG2 | power_out | Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V). |+| 35 | REG1 | power_out | Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V). |+| 36 | REGIN | input | Analog input pin for REG1 and REG2 LDO preregulator control. |+| 37 | BREG | tri_state | Open-drain output for external NPN BJT base control in preregulator circuit. |+| 38 | FUSE | bidirectional | Open-drain fuse sense and drive pin for secondary protector circuit integration. |+| 39 | PDSG | tri_state | Open-drain output for predischarge PFET gate drive control. |+| 40 | PCHG | tri_state | Open-drain output for precharge PFET gate drive control. |+| 41 | LD | bidirectional | Open-drain I/O pin for load detect functionality and sensing. |+| 42 | PACK | input | Analog input pin for pack sense voltage measurement. |+| 43 | DSG | tri_state | Open-drain NFET discharge driver output pin for battery pack discharge control. |+| 44 | NC | unconnected | This pin is not connected to silicon. |+| 45 | CHG | tri_state | Open-drain NFET charge driver output pin for battery pack charge control. |+| 46 | CP1 | bidirectional | Charge pump capacitor connection for integrated high-side NFET gate drive. |+| 47 | BAT | power_in | Primary power supply input pin, connected to top of battery stack. |+| 48 | VC10 | input | Sense voltage input and balance current input for tenth cell, top-of-stack measurement point. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-48(7x7) |+| Category | Power Management (PMIC) |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `BQ7694202PFBR`+- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`+- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `bq7694202pfbr-etched.step` / `bq7694202pfbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq7694202pfbr.step` / `bq7694202pfbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq76942) (85 pp, sha256 `a976a88e92abb957`, retrieved 2026-09-23, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq7694202pfbr-datasheet.pdf)
page.jsonadded+381@@ -0,0 +1,381 @@+{+ "slug": "bq7694202pfbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Battery Management, TQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "bq7694202pfbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "bq7694202pfbr.kicad_sym",+ "bq7694202pfbr.kicad_mod",+ "bq7694202pfbr.glb",+ "bq7694202pfbr.step",+ "bq7694202pfbr.lbr",+ "docs/hero.png",+ "docs/bq7694202pfbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "BQ7694202PFBR",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-48(7x7)",+ "pin_count": 48,+ "category": "Power Management (PMIC)",+ "subcategory": "Battery Management",+ "datasheet": "https://www.ti.com/cn/lit/gpn/bq76942",+ "parts": {+ "symbol": "bq7694202pfbr.kicad_sym",+ "footprint": "bq7694202pfbr.kicad_mod",+ "model_3d": "bq7694202pfbr-etched.glb",+ "model_3d_plain": "bq7694202pfbr.glb",+ "model_3d_step": "bq7694202pfbr-etched.step",+ "model_3d_step_plain": "bq7694202pfbr.step",+ "lbr": "bq7694202pfbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C3682863"+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "2",+ "name": "VC9",+ "type": "input",+ "description": "Sense voltage input and balance current input for the ninth cell from the bottom of the stack."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "4",+ "name": "VC8",+ "type": "input",+ "description": "Sense voltage input and balance current input for the eighth cell from the bottom of the stack."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "6",+ "name": "VC7",+ "type": "input",+ "description": "Sense voltage input and balance current input for the seventh cell from the bottom of the stack."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "8",+ "name": "VC6",+ "type": "input",+ "description": "Sense voltage input and balance current input for the sixth cell from the bottom of the stack."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "10",+ "name": "VC5",+ "type": "input",+ "description": "Sense voltage input and balance current input for the fifth cell from the bottom of the stack."+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "12",+ "name": "VC4",+ "type": "input",+ "description": "Sense voltage input and balance current input for the fourth cell from the bottom of the stack."+ },+ {+ "number": "13",+ "name": "VC3",+ "type": "input",+ "description": "Sense voltage input and balance current input for the third cell from the bottom of the stack."+ },+ {+ "number": "14",+ "name": "VC2",+ "type": "input",+ "description": "Sense voltage input and balance current input for the second cell from the bottom of the stack."+ },+ {+ "number": "15",+ "name": "VC1",+ "type": "input",+ "description": "Sense voltage input and balance current input for the first cell from the bottom of the stack."+ },+ {+ "number": "16",+ "name": "VC0",+ "type": "input",+ "description": "Sense voltage input for negative terminal of the first cell and return balance current."+ },+ {+ "number": "17",+ "name": "VSS",+ "type": "power_in",+ "description": "Device ground."+ },+ {+ "number": "18",+ "name": "SRP",+ "type": "input",+ "description": "Analog input to coulomb counter for integrating differential voltage across sense resistor, positive terminal."+ },+ {+ "number": "19",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "20",+ "name": "SRN",+ "type": "input",+ "description": "Analog input to coulomb counter for integrating differential voltage across sense resistor, negative terminal."+ },+ {+ "number": "21",+ "name": "TS1",+ "type": "bidirectional",+ "description": "Thermistor input or general purpose ADC/digital output pin."+ },+ {+ "number": "22",+ "name": "TS2",+ "type": "bidirectional",+ "description": "Thermistor input with wakeup from SHUTDOWN capability or general purpose ADC/digital output pin."+ },+ {+ "number": "23",+ "name": "TS3",+ "type": "bidirectional",+ "description": "Thermistor input or general purpose ADC/digital output pin."+ },+ {+ "number": "24",+ "name": "REG18",+ "type": "power_out",+ "description": "Internal 1.8 V LDO output for internal device use only."+ },+ {+ "number": "25",+ "name": "ALERT",+ "type": "bidirectional",+ "description": "Multifunction pin for ALERT output, HDQ interface, thermistor input, ADC input, or digital output."+ },+ {+ "number": "26",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C clock or SPI clock interface pin."+ },+ {+ "number": "27",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C data or SPI MISO interface pin."+ },+ {+ "number": "28",+ "name": "HDQ",+ "type": "bidirectional",+ "description": "HDQ single-wire, SPI MOSI interface, or multifunction ADC/digital pin."+ },+ {+ "number": "29",+ "name": "CFETOFF",+ "type": "bidirectional",+ "description": "Charge FET control, SPI chip select, or multifunction ADC/digital pin."+ },+ {+ "number": "30",+ "name": "DFETOFF",+ "type": "bidirectional",+ "description": "Discharge FET control, BOTHOFF, or multifunction ADC/digital pin."+ },+ {+ "number": "31",+ "name": "DCHG",+ "type": "bidirectional",+ "description": "Charge FET fault signal output or general purpose ADC/digital output pin."+ },+ {+ "number": "32",+ "name": "DDSG",+ "type": "bidirectional",+ "description": "Discharge FET fault signal output or general purpose ADC/digital output pin."+ },+ {+ "number": "33",+ "name": "RST_SHUT",+ "type": "input",+ "description": "Digital input pin for device reset or shutdown control."+ },+ {+ "number": "34",+ "name": "REG2",+ "type": "power_out",+ "description": "Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V)."+ },+ {+ "number": "35",+ "name": "REG1",+ "type": "power_out",+ "description": "Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V)."+ },+ {+ "number": "36",+ "name": "REGIN",+ "type": "input",+ "description": "Analog input pin for REG1 and REG2 LDO preregulator control."+ },+ {+ "number": "37",+ "name": "BREG",+ "type": "tri_state",+ "description": "Open-drain output for external NPN BJT base control in preregulator circuit."+ },+ {+ "number": "38",+ "name": "FUSE",+ "type": "bidirectional",+ "description": "Open-drain fuse sense and drive pin for secondary protector circuit integration."+ },+ {+ "number": "39",+ "name": "PDSG",+ "type": "tri_state",+ "description": "Open-drain output for predischarge PFET gate drive control."+ },+ {+ "number": "40",+ "name": "PCHG",+ "type": "tri_state",+ "description": "Open-drain output for precharge PFET gate drive control."+ },+ {+ "number": "41",+ "name": "LD",+ "type": "bidirectional",+ "description": "Open-drain I/O pin for load detect functionality and sensing."+ },+ {+ "number": "42",+ "name": "PACK",+ "type": "input",+ "description": "Analog input pin for pack sense voltage measurement."+ },+ {+ "number": "43",+ "name": "DSG",+ "type": "tri_state",+ "description": "Open-drain NFET discharge driver output pin for battery pack discharge control."+ },+ {+ "number": "44",+ "name": "NC",+ "type": "unconnected",+ "description": "This pin is not connected to silicon."+ },+ {+ "number": "45",+ "name": "CHG",+ "type": "tri_state",+ "description": "Open-drain NFET charge driver output pin for battery pack charge control."+ },+ {+ "number": "46",+ "name": "CP1",+ "type": "bidirectional",+ "description": "Charge pump capacitor connection for integrated high-side NFET gate drive."+ },+ {+ "number": "47",+ "name": "BAT",+ "type": "power_in",+ "description": "Primary power supply input pin, connected to top of battery stack."+ },+ {+ "number": "48",+ "name": "VC10",+ "type": "input",+ "description": "Sense voltage input and balance current input for tenth cell, top-of-stack measurement point."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 85,+ "cost_usd": 1.0293,+ "at": "2026-09-23T12:26:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/bq76942",+ "pages": 85,+ "sha256": "a976a88e92abb957",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}