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BQ7694202PFBR

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Texas Instruments Battery Management, TQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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BQ7694202PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7694202PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected This pin is not connected to silicon.
2 VC9 input Sense voltage input and balance current input for the ninth cell from the bottom of the stack.
3 NC unconnected This pin is not connected to silicon.
4 VC8 input Sense voltage input and balance current input for the eighth cell from the bottom of the stack.
5 NC unconnected This pin is not connected to silicon.
6 VC7 input Sense voltage input and balance current input for the seventh cell from the bottom of the stack.
7 NC unconnected This pin is not connected to silicon.
8 VC6 input Sense voltage input and balance current input for the sixth cell from the bottom of the stack.
9 NC unconnected This pin is not connected to silicon.
10 VC5 input Sense voltage input and balance current input for the fifth cell from the bottom of the stack.
11 NC unconnected This pin is not connected to silicon.
12 VC4 input Sense voltage input and balance current input for the fourth cell from the bottom of the stack.
13 VC3 input Sense voltage input and balance current input for the third cell from the bottom of the stack.
14 VC2 input Sense voltage input and balance current input for the second cell from the bottom of the stack.
15 VC1 input Sense voltage input and balance current input for the first cell from the bottom of the stack.
16 VC0 input Sense voltage input for negative terminal of the first cell and return balance current.
17 VSS power_in Device ground.
18 SRP input Analog input to coulomb counter for integrating differential voltage across sense resistor, positive terminal.
19 NC unconnected This pin is not connected to silicon.
20 SRN input Analog input to coulomb counter for integrating differential voltage across sense resistor, negative terminal.
21 TS1 bidirectional Thermistor input or general purpose ADC/digital output pin.
22 TS2 bidirectional Thermistor input with wakeup from SHUTDOWN capability or general purpose ADC/digital output pin.
23 TS3 bidirectional Thermistor input or general purpose ADC/digital output pin.
24 REG18 power_out Internal 1.8 V LDO output for internal device use only.
25 ALERT bidirectional Multifunction pin for ALERT output, HDQ interface, thermistor input, ADC input, or digital output.
26 SCL bidirectional I2C clock or SPI clock interface pin.
27 SDA bidirectional I2C data or SPI MISO interface pin.
28 HDQ bidirectional HDQ single-wire, SPI MOSI interface, or multifunction ADC/digital pin.
29 CFETOFF bidirectional Charge FET control, SPI chip select, or multifunction ADC/digital pin.
30 DFETOFF bidirectional Discharge FET control, BOTHOFF, or multifunction ADC/digital pin.
31 DCHG bidirectional Charge FET fault signal output or general purpose ADC/digital output pin.
32 DDSG bidirectional Discharge FET fault signal output or general purpose ADC/digital output pin.
33 RST_SHUT input Digital input pin for device reset or shutdown control.
34 REG2 power_out Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V).
35 REG1 power_out Programmable LDO output (1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V).
36 REGIN input Analog input pin for REG1 and REG2 LDO preregulator control.
37 BREG tri_state Open-drain output for external NPN BJT base control in preregulator circuit.
38 FUSE bidirectional Open-drain fuse sense and drive pin for secondary protector circuit integration.
39 PDSG tri_state Open-drain output for predischarge PFET gate drive control.
40 PCHG tri_state Open-drain output for precharge PFET gate drive control.
41 LD bidirectional Open-drain I/O pin for load detect functionality and sensing.
42 PACK input Analog input pin for pack sense voltage measurement.
43 DSG tri_state Open-drain NFET discharge driver output pin for battery pack discharge control.
44 NC unconnected This pin is not connected to silicon.
45 CHG tri_state Open-drain NFET charge driver output pin for battery pack charge control.
46 CP1 bidirectional Charge pump capacitor connection for integrated high-side NFET gate drive.
47 BAT power_in Primary power supply input pin, connected to top of battery stack.
48 VC10 input Sense voltage input and balance current input for tenth cell, top-of-stack measurement point.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ7694202PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq7694202pfbr-etched.step / bq7694202pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7694202pfbr.step / bq7694202pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 a976a88e92abb957, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF