Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	6h ago
viewers	bq7694201pfbr: viewers · Ray	6h ago
bq7694201pfbr-etched.glb	bq7694201pfbr: factory component page (tier=lcsc) · Ray	6h ago
bq7694201pfbr-etched.step	bq7694201pfbr: factory component page (tier=lcsc) · Ray	6h ago
bq7694201pfbr-hero.glb	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr-hero.overlay.json	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr.glb	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr.kicad_mod	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr.kicad_sym	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr.lbr	Publish 0.1.0 · Ray	6h ago
bq7694201pfbr.step	Publish 0.1.0 · Ray	6h ago
package.json	Publish 0.1.0 · Ray	6h ago
page.json	Set visibility: public · Ray	6h ago
README.md	Initial commit: component/bq7694201pfbr · Ray	6h ago

BQ7694201PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7694201PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	This pin is not connected to silicon.
2	VC9	input	Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack
3	NC	unconnected	This pin is not connected to silicon.
4	VC8	input	Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack
5	NC	unconnected	This pin is not connected to silicon.
6	VC7	input	Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack and return balance current for the eighth cell from the bottom of the stack
7	NC	unconnected	This pin is not connected to silicon.
8	VC6	input	Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack
9	NC	unconnected	This pin is not connected to silicon.
10	VC5	input	Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack
11	NC	unconnected	This pin is not connected to silicon.
12	VC4	input	Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
13	VC3	input	Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
14	VC2	input	Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
15	VC1	input	Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
16	VC0	input	Sense voltage input pin for negative terminal of the first cell from the bottom of the stack, and return balance current for first cell from the bottom of the stack
17	VSS	power_in	Device ground
18	SRP	input	Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
19	NC	unconnected	This pin is not connected to silicon.
20	SRN	input	Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
21	TS1	bidirectional	Thermistor input, or general purpose ADC input
22	TS2	bidirectional	Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input
23	TS3	bidirectional	Thermistor input, or general purpose ADC input
24	REG18	power_out	Internal 1.8 V-LDO output (only for internal use)
25	ALERT	bidirectional	Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output
26	SCL	bidirectional	Multifunction pin, can be SCL or SPI_SCLK
27	SDA	bidirectional	Multifunction pin, can be SDA or SPI_MISO
28	HDQ	bidirectional	Multifunction pin, can be HDQ I/O, or SPI_MOSI, or thermistor input, or general purpose ADC input, or general purpose digital output
29	CFETOFF	bidirectional	Multifunction pin, can be CFETOFF, or SPI_CS, or thermistor input, or general purpose ADC input, or general purpose digital output
30	DFETOFF	bidirectional	Multifunction pin, can be DFETOFF or BOTHOFF, or thermistor input, or general purpose ADC input, or general purpose digital output
31	DCHG	bidirectional	Multifunction pin, can be DCHG, or thermistor input, or general purpose ADC input, or general purpose digital output
32	DDSG	bidirectional	Multifunction pin, can be DDSG, or thermistor input, or general purpose ADC input, or general purpose digital output
33	RST_SHUT	input	Digital input pin for reset or shutdown
34	REG2	power_out	Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
35	REG1	power_out	First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V
36	REGIN	input	Input pin for REG1 and REG2 LDOs
37	BREG	output	Base control signal for external preregulator transistor
38	FUSE	bidirectional	Fuse sense and drive
39	PDSG	output	Predischarge PFET control
40	PCHG	output	Precharge PFET control
41	LD	bidirectional	Load detect pin
42	PACK	input	Pack sense input pin
43	DSG	output	NMOS discharge FET drive output pin
44	NC	unconnected	This pin is not connected to silicon.
45	CHG	output	NMOS charge FET drive output pin
46	CP1	bidirectional	Charge pump capacitor
47	BAT	power_in	Primary power supply input pin
48	VC10	input	Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and top-of-stack measurement point

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-48(7x7)
Category	Power Management (PMIC)
Pins	48

CAD (KiCad official)

Symbol: BQ7694201PFBR
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: bq7694201pfbr-etched.step / bq7694201pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7694201pfbr.step / bq7694201pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (85 pp, sha256 a976a88e92abb957, retrieved 2026-10-06, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF