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Contents

README

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BQ7692006PWR

Texas Instruments · Battery Management · TSSOP-20

BQ7692006PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DSG output Discharge FET driver output with 0-16 V range and 12 V nominal pull-up when enabled via DSG_ON register bit.
2 CHG output Charge FET driver output with 0-16 V range, 18-22 V clamp voltage, and 12 V nominal pull-up when enabled via CHG_ON register bit.
3 VSS power_in Chip ground reference pin; all voltages measured relative to this pin except cell differentials.
4 SDA bidirectional I2C serial data pin with open-drain output and input threshold of REGOUT × 0.25 to REGOUT × 0.75 V.
5 SCL input I2C serial clock input for 100 kHz communication with input threshold of REGOUT × 0.25 to REGOUT × 0.75 V.
6 TS1 input Thermistor #1 positive input with 10 kΩ internal pull-up; must be pulled down to VSS with 10 kΩ nominal resistor if unused.
7 CAP1 output Output node for LDO capacitor connection to VSS; requires 1-4.7 µF capacitor for LDO ripple filtering.
8 REGOUT power_out Output LDO pin providing 2.5 V or 3.3 V (factory programmed) with output voltage range of 0-3.6 V.
9 REGSRC power_in Input source pin for external LDO, accepts 6-25 V supply voltage.
10 BAT power_in Battery (top-most) terminal supply pin accepting 6-25 V nominal for 3-5 series cell configurations.
11 NC unconnected No connect pin; do not connect to any signal.
12 VC5 input 5th cell positive terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
13 VC4 input 4th cell positive terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
14 VC3 input 3rd cell positive terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
15 VC2 input 2nd cell positive terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
16 VC1 input 1st cell positive terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
17 VC0 input 1st cell negative terminal voltage sense input with 0-5 V differential range, measured by 14-bit ADC with 382 µV LSB.
18 SRP input Negative current sense input (nearest VSS) with -10 to 10 mV operating range for OCD/SCD protection.
19 SRN input Positive current sense input with -200 to 200 mV operating range for 16-bit coulomb counter measurement.
20 ALERT bidirectional Alert output (active high) and external override input pin; external pull-down of 500 kΩ to 1 MΩ to VSS recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Power Management (PMIC)
Pins 20

CAD (KiCad official)

  • Symbol: BQ7692006PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: bq7692006pwr-etched.step / bq7692006pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7692006pwr.step / bq7692006pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 9ddaaac2ca3b2ca1, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF