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BQ769142PFBR

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Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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BQ769142PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ769142PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VC13A input Return balance current for the fourteenth cell from the bottom of the stack; this pin should be shorted to VC13B on the PCB.
2 VC13B input Sense voltage input for the thirteenth cell from the bottom of the stack and balance current input for that cell.
3 VC12A input Return balance current for the thirteenth cell from the bottom of the stack; this pin should be shorted to VC12B on the PCB.
4 VC12B input Sense voltage input for the twelfth cell from the bottom of the stack and balance current input for that cell.
5 VC11 input Sense voltage input and balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell.
6 VC10 input Sense voltage input and balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell.
7 VC9 input Sense voltage input and balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell.
8 VC8 input Sense voltage input and balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell.
9 VC7 input Sense voltage input and balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell.
10 VC6 input Sense voltage input and balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell.
11 VC5 input Sense voltage input and balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell.
12 VC4 input Sense voltage input and balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell.
13 VC3 input Sense voltage input and balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell.
14 VC2 input Sense voltage input and balance current input for the second cell from the bottom of the stack, and return balance current for the third cell.
15 VC1 input Sense voltage input and balance current input for the first cell from the bottom of the stack, and return balance current for the second cell.
16 VC0 input Sense voltage input for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell.
17 VSS power_in Device ground.
18 SRP input Analog input to the coulomb counter for the top of the sense resistor; a charging current produces a positive voltage at SRP relative to SRN, and the differential voltage must stay within the ±200 mV range for current measurement.
19 NC unconnected This pin is not connected to silicon.
20 SRN input Analog input to the coulomb counter for the bottom of the sense resistor, paired with SRP for differential pack current measurement.
21 TS1 bidirectional Thermistor input or general-purpose ADC input (open-drain digital I/O with analog I/O capability).
22 TS2 bidirectional Thermistor input that also functions as wakeup from SHUTDOWN, or general-purpose ADC input; should be left floating if the device is intended to enter SHUTDOWN mode.
23 TS3 bidirectional Thermistor input or general-purpose ADC input (open-drain digital I/O with analog I/O capability).
24 REG18 power_out Internal 1.8-V LDO output, for internal use only; regulator voltage is specified at 1.6 V to 2 V.
25 ALERT bidirectional Multifunction pin that can be configured as ALERT output, HDQ I/O, thermistor input, general-purpose ADC input, or general-purpose digital output.
26 SCL bidirectional Multifunction pin that can be configured as I2C SCL or SPI_SCLK; I2C supports speeds up to 400 kHz.
27 SDA bidirectional Multifunction pin that can be configured as I2C SDA or SPI_MISO.
28 HDQ bidirectional Multifunction pin that can be configured as HDQ I/O, SPI_MOSI, thermistor input, general-purpose ADC input, or general-purpose digital output.
29 CFETOFF bidirectional Multifunction pin that can be configured as CFETOFF input (disables CHG and PCHG FETs when asserted), SPI_CS, thermistor input, general-purpose ADC input, or general-purpose digital output.
30 DFETOFF bidirectional Multifunction pin that can be configured as DFETOFF input (disables DSG and PDSG FETs when asserted), BOTHOFF, thermistor input, general-purpose ADC input, or general-purpose digital output.
31 DCHG bidirectional Multifunction pin that can be configured as DCHG fault output, thermistor input, general-purpose ADC input, or general-purpose digital output.
32 DDSG bidirectional Multifunction pin that can be configured as DDSG fault output, thermistor input, general-purpose ADC input, or general-purpose digital output.
33 RST_SHUT input Digital input for reset or shutdown; driving it high resets most digital logic, and holding it high for 1 second transitions the device into SHUTDOWN mode.
34 REG2 power_out Second LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
35 REG1 power_out First LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
36 REGIN input Input pin for the REG1 and REG2 LDOs.
37 BREG output Base control signal for an external preregulator transistor.
38 FUSE bidirectional Fuse sense and drive pin; can drive the gate of an NFET to blow a chemical fuse and detects an externally applied high signal when not asserted.
39 PDSG output Predischarge PFET control output.
40 PCHG output Precharge PFET control output.
41 LD bidirectional Load detect pin, with an internal pullup from BAT used for load detect functionality.
42 PACK input Pack sense input pin.
43 DSG output NMOS discharge FET drive output.
44 NC unconnected This pin is not connected to silicon.
45 CHG output NMOS charge FET drive output.
46 CP1 bidirectional Charge pump capacitor pin; if not used, it should be connected to BAT (pin 47).
47 BAT power_in Primary power supply input pin; the device draws its supply current from this pin, with supply range up to 85 V absolute maximum.
48 VC14 input Sense voltage input, balance current input, and top-of-stack measurement point for the fourteenth cell from the bottom of the stack.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ769142PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq769142pfbr-etched.step / bq769142pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq769142pfbr.step / bq769142pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 7a43e8e4f6778954, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF