component

BQ33100PWR

Public Made by Adom

by adom

Texas Instruments Battery Management, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)bq33100pwrfactory-2.0.0extractor-text

Verified BQ33100PWR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: BQ33100PWR · TSSOP-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 67-page datasheet
  • ✓distributor: lcsc C181244, digikey 296-28422-2-ND, mouser 595-BQ33100PWR
  • ✓family: TSSOP-24_4.4x7.8mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-u7fu0gwl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ bq33100pwr.kicad_sym✓ bq33100pwr.kicad_mod✓ bq33100pwr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 1d ago
viewers bq33100pwr: viewers · Ray 1d ago
bq33100pwr-etched.glb Publish 0.1.0 · Ray 1d ago
bq33100pwr-etched.step bq33100pwr: factory component page (tier=mfr) · Ray 1d ago
bq33100pwr-hero.glb bq33100pwr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
bq33100pwr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
bq33100pwr.glb Publish 0.1.0 · Ray 1d ago
bq33100pwr.kicad_mod Publish 0.1.0 · Ray 1d ago
bq33100pwr.kicad_sym Publish 0.1.0 · Ray 1d ago
bq33100pwr.lbr Publish 0.1.0 · Ray 1d ago
bq33100pwr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 24 pins · Ray 1d ago

BQ33100PWR

Texas Instruments · Battery Management · TSSOP-24

BQ33100PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCCPACK power_in Power supply from the super capacitors; the top of the super capacitor stack must be connected to this pin.
2 NC unconnected Not used and must be connected to VCC.
3 VC1 input Sense voltage input terminal and external capacitor voltage balancing drive output for the 5th-series capacitor, and stack measurement input.
4 VC2 input Sense voltage input terminal and external capacitor voltage balancing drive output for the 4th-series capacitor.
5 VC3 input Sense voltage input terminal and external capacitor voltage balancing drive output for the 3rd-series capacitor.
6 VC4 input Sense voltage input terminal and external capacitor voltage balancing drive output for the 2nd-series capacitor.
7 SRP input Analog input for the internal ADC measuring the small voltage between SRP and SRN, where SRP is the top of the sense resistor.
8 SRN input Analog input for the internal ADC measuring the small voltage between SRP and SRN, where SRN is the bottom of the sense resistor.
9 TS input Thermistor input.
10 VC5 input Sense voltage input terminal and external capacitor voltage balancing drive output for the 1st capacitor.
11 CHGLVL0 output Charge control output 0.
12 CHGLVL1 output Charge control output 1.
13 VC5BAL output Cell balance control output for the least positive capacitor, used only in a 5-series capacitor configuration.
14 SDA bidirectional Serial data line that transmits and receives data (open-drain).
15 FAULT output Active high output to indicate fault condition.
16 SCL bidirectional Serial clock input that clocks data on SDA (open-drain).
17 LLEN output Learn Load Enable output.
18 RBI power_in RAM backup pin providing backup potential to the internal DATA RAM if power is momentarily lost, via a capacitor attached between RBI and GND.
19 GND power_in Ground.
20 REG27 power_out Internal power supply 2.7-V bias output, requiring an external 1 µF capacitor.
21 CHGOR input CHG override input; if not used, connect to VSS.
22 NC unconnected No connect; leave the NC pin floating.
23 CHG output P-channel FET drive for controlling charge.
24 VCC power_in Positive input from power supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Power Management (PMIC)
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC w.r.t. GND VMAX -0.3 34 V 5
Input voltage SDA, SCL VIN -0.3 6 V 5
Input voltage RBI, REG27 VIN -0.3 2.75 V 5
Maximum combined sink current for input pins ISS 50 mA 5
Functional temperature TFUNC -40 110 °C 5
Storage temperature Tstg -65 150 °C 5
Supply voltage VCC VCC 25 V 6
Supply voltage VCC VCC 3.8 V 6
Start up voltage at VCC VSTARTUP 5.2 5.5 V 6
Shutdown voltage VCC or VCCPACK, whichever is higher VSHUTDOWN 3 3.2 3.3 V VCC or VCCPACK, whichever is higher 6
Cell voltage difference VCn, VC(n+1) 0 5 V n=1, 2, 3, 4 6
Input voltage VC5 VC5 0 1 V 6
Input voltage CHGOR CHGOR 0 V 6
Input voltage SRP to SRN -0.3 1 V 6
Operating temperature TOPR -40 85 °C 6
High-level input voltage SDA, SCL, TS, VC5 VIH 2 V 6
Low-level input voltage SDA, SCL, TS, VC5 VIL 0.8 V 6
Low-level output voltage SDA, SCL, VC5BAL, CHGLVL0, CHGLVL1, LLEN, FAULT VOL 0.4 V IL = 7 mA 6
CHG override active high VCHGOR 0.8 2 3.2 V 6
SDA and SCL pulldown RPD(SMBx) 600 950 1300 kΩ TA = -40°C to 100°C 6
Pad resistance TS RPAD 87 110 Ω 6
NORMAL mode supply current ICC ICC 660 µA Firmware running, no flash writes 7
SHUTDOWN mode supply current ISHUTDOWN 0.5 1 µA TA = -40°C to 110°C 7
Regulator output voltage VREG 2.5 2.7 2.75 V IREG27 = 10 mA TA = -40°C to 85°C 7
Negative-going POR voltage VREG27IT- 2.22 2.35 2.34 V At REG27 7
Positive-going POR voltage VREG27IT+ 2.25 2.5 2.6 V At REG27 7
Regulator output change with temperature ΔV(REGTEMP) -0.5 0.5 % IREG = 10 mA TA = -40°C to 85°C 7
Line regulation ΔV(REGLINE) -4 4 mV IREG = 10 mA 7
Load regulation ΔV(REGLOAD) -40 40 mV IREG = 0.2 to 10 mA 7
Current limit I(REGMAX) 25 50 mA 7
Coulomb counter input voltage range -0.2 0.25 V 7
Coulomb counter integral nonlinearity -0.034 0.034 % FSR TA = -25°C to 85°C 7
Coulomb counter offset error drift 0.3 0.5 µV/°C 7
Coulomb counter full-scale error -0.8 0.2 0.8 % 7
ADC input voltage range TS, VC5 -0.2 V 7
ADC effective resolution 14 15 Bits 7
ADC integral nonlinearity -0.02 0.02 % FSR 7
ADC offset error 70 160 µV 7
ADC full-scale error -0.8 0.2 0.4 % VIN = 1 V 7
SMBus operating frequency fSMB 10 100 kHz Slave mode, SCL 50% duty cycle 11
Bus free time between start and stop tBUF 4.7 µs 11
Hold time after (repeated) start tHD:STA 4 µs 11
Repeated start setup time tSU:STA 4.7 µs 11
Stop setup time tSU:STO 4 µs 11
Data hold time tHD:DAT 0 ns Receive mode 11
Data hold time tHD:DAT 300 ns Transmit mode 11
Data setup time tSU:DAT 250 ns 11
Error signal and detect timeout tTIMEOUT 25 35 ms Error signal and detect 11
Clock low period tLOW 4.7 µs 11
Clock high period tHIGH 4 50 µs 11
Cumulative clock low slave extend time tLOW:SEXT 25 ms 11
Cumulative clock low master extend time tLOW:MEXT 10 ms 11
Clock and data fall time tF 300 ns 11
Clock and data rise time tR 1000 ns 11
Junction-to-ambient thermal resistance RθJA 83.6 °C/W 6
Junction-to-case (top) thermal resistance RθJC(top) 16.5 °C/W 6
Junction-to-board thermal resistance RθJB 39.4 °C/W 6
Junction-to-top characterization parameter ψJT 0.4 °C/W 6
Junction-to-board characterization parameter ψJB 38.8 °C/W 6

CAD (KiCad official)

  • Symbol: BQ33100PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: bq33100pwr-etched.step / bq33100pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq33100pwr.step / bq33100pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (67 pp, sha256 00490ad38b152ebb, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF