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BQ296107DSGR

Texas Instruments · Battery Management ICs · WSON-8-EP(2x2)

BQ296107DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input, recommended 3 V to 20 V (4 V minimum with REG output on), absolute maximum 30 V with respect to VSS.
2 V4 input Sense input for the positive voltage of the fourth cell from the bottom of the stack, with 0 V to 5 V recommended cell voltage (V4 - V3) and 30 V absolute maximum.
3 V3 input Sense input for the positive voltage of the third cell from the bottom of the stack, with 0 V to 5 V recommended cell voltage (V3 - V2) and 30 V absolute maximum.
4 V2 input Sense input for the positive voltage of the second cell from the bottom of the stack, with 0 V to 5 V recommended cell voltage (V2 - V1) and 30 V absolute maximum.
5 V1 input Sense input for the positive voltage of the lowest cell from the bottom of the stack, with 0 V to 5 V recommended cell voltage (V1 - VSS) and 30 V absolute maximum.
6 VSS power_in Electrically connected to integrated circuit ground and the negative terminal of the lowest cell in the stack.
7 REG power_out Regulated supply output (3.3 V option for BQ296107, up to 2 mA) that requires an external ceramic capacitor for stability, with absolute maximum 3.6 V with respect to VSS.
8 OUT output Analog output drive for the overvoltage fault signal, asserted after the 6.5 s delay when a cell exceeds the 4.50 V OVP threshold, CMOS output high or open-drain active low, absolute maximum 30 V with respect to VSS.
9 PWPD passive Exposed thermal pad, which TI recommends connecting to VSS on the PCB.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8-EP(2x2)
Category Power Supply Chip
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
OV detection hysteresis VHYS 250 300 400 mV 6
OV detection accuracy VOA -10 10 mV TA = 25°C 6
OV detection accuracy across temperature VOADRIFT -40 40 mV TA = -40°C 6
OV detection accuracy across temperature VOADRIFT -20 20 mV TA = 0°C 6
OV detection accuracy across temperature VOADRIFT -24 24 mV TA = 60°C 6
OV detection accuracy across temperature VOADRIFT -54 54 mV TA = 110°C 6
Supply current with REG on IDD 4 6 µA (Vn, Vn-1) = 2 V to 4.15 V, (V1, VSS) > VUVREG, IREG = 0 mA, TA = 0°C to 60°C 6
Supply current with REG on IDD 8 µA TA = -40°C to 110°C 6
Supply current with REG off IDD 1 2 µA (V1, VSS) < VUVREG, TA = 0°C to 60°C 6
Supply current with REG off IDD 4 µA TA = -40°C to 110°C 6
Input current at Vx pins IIN -0.1 0.1 µA (Vn, Vn-1) = (V1, VSS) = 3.8 V, VDD = top Vn voltage, TA = 25°C 6
Output drive voltage, active high VOUT 6 7 8 V (Vn, Vn-1) or (V1, VSS) > VOV, IOH = 100 µA, VDD = top Vn voltage 6
OUT sink current (no OV) IOUTL 0.5 14 mA forced OUT = VDD, RPU = 5 kΩ to VDD 6
OV delay time, 6.5-s option tDELAY 5.2 6.5 7.8 s Internal Fixed Delay, 6.5-s delay option 6
REG supply at 500 µA load VREG 3.234 3.3 3.366 V VDD ≥ 4 V, IREG = 500 µA, CREG = 0.47 µF, VREG = 3.3 V 7
REG supply from 0 to 2 mA load VREG 3.2 3.3 3.4 V VDD ≥ 4 V, IREG = 0 µA to 2 mA, CREG = 0.47 µF, VREG = 3.3 V 7
REG current output IREG 0 2 mA VDD ≥ 4 V, CREG = 0.47 µF 7
REG pull-down resistor RREG_PD 20 30 45 kΩ REG is disabled 7
Undervoltage detection VUVREG -50 50 mV Factory Configuration: 2.0 V to 3.5 V in 50 mV steps, TA = 25°C 7
Undervoltage detection hysteresis VUVHYS 250 300 400 mV 7
Undervoltage detection delay tUVDELAY 4.5 6 7.5 s 7
Supply voltage VDD, VSS -0.3 30 V 5
Input voltage between cell pins V4-V3, V3-V2, V2-V1, V1-VSS -0.3 30 V 5
REG voltage REG, VSS -0.3 3.6 V 5
Output voltage OUT, VSS -0.3 30 V 5
Lead temperature TSOLDER 300 300 °C soldering, 10 s 5
Storage temperature Tstg -65 150 °C 5
Supply voltage VDD 3 20 V 5
Supply voltage with REG output on VDD 4 V REG output on 5
Input voltage range Vn, Vn-1, V1, VSS 0 5 V 5
Operating ambient temperature range TA -40 110 °C 5
Junction-to-ambient thermal resistance RθJA 62 °C/W DSG (WSON) 8 pins 5
Junction-to-case(top) thermal resistance RθJC(top) 72 °C/W DSG (WSON) 8 pins 5
Junction-to-board thermal resistance RθJB 32.5 °C/W DSG (WSON) 8 pins 5
Junction-to-top characterization parameter ψJT 1.6 °C/W DSG (WSON) 8 pins 5
Junction-to-board characterization parameter ψJB 33 °C/W DSG (WSON) 8 pins 5
Junction-to-case(bottom) thermal resistance RθJC(bot) 10 °C/W DSG (WSON) 8 pins 5
ESD HBM V(ESD) 2000 V Human body model, ANSI/ESDA/JEDEC JS-001 5
ESD CDM V(ESD) 500 V Charged device model, JESD22-C101 5

CAD (KiCad official)

  • Symbol: BQ296107DSGR
  • Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
  • 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: bq296107dsgr-etched.step / bq296107dsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq296107dsgr.step / bq296107dsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 c7f5c04460f60672, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF