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Initial commit: component/bq294701dsgr

Ray ·2b2d191dcc ·2d ago
2 files changed +252
README.mdadded+46
@@ -0,0 +1,46 @@+# BQ294701DSGR++**Texas Instruments** · Battery Management · WSON-8-EP(2x2)++BQ294701DSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD | power_in | Unregulated IC supply input, recommended 3 V to 20 V (VDD-VSS) with absolute maximum 30 V; a series resistor limits current and a capacitor to ground filters noise. |+| 2 | V4 | input | Sense input for the positive voltage of the fourth (top) cell in the stack, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input. |+| 3 | V3 | input | Sense input for the positive voltage of the third cell from the bottom, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input. |+| 4 | V2 | input | Sense input for the positive voltage of the second cell from the bottom, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input. |+| 5 | V1 | input | Sense input for the positive voltage of the bottom cell in the stack, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input. |+| 6 | VSS | power_in | IC ground, connected to the negative terminal of the bottom cell; absolute maximum rating −0.3 V to 30 V relative to VSS for the other pins. |+| 7 | CD | output | External delay capacitor connection that sets the overvoltage delay tCD = K × CCD (K = 10 to 20 s/µF, so 0.1 µF gives 1 s to 2 s); shorting CD to VSS enables the customer test mode with delay of 170 ms maximum. |+| 8 | OUT | output | Overvoltage fault signal output, factory-set as CMOS active-high or open-drain active-low; the open-drain version requires an external pull-up resistor and absolute maximum is 30 V to VSS. |+| 9 | PowerPAD | power_in | Exposed thermal pad that TI recommends connecting to VSS on the PCB and that must be soldered to the board for thermal and mechanical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WSON-8-EP(2x2) |+| Category | Power Management (PMIC) |+| Pins | 9 |++## CAD (KiCad official)++- Symbol: `BQ294701DSGR`+- Footprint: `Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm`+- 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)+- 3D model files: `bq294701dsgr-etched.step` / `bq294701dsgr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq294701dsgr.step` / `bq294701dsgr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq2947) (30 pp, sha256 `0bb66de94396f561`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/bq294701dsgr-datasheet.pdf)
page.jsonadded+206
@@ -0,0 +1,206 @@+{+  "slug": "bq294701dsgr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Battery Management, WSON-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "bq294701dsgr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "bq294701dsgr.kicad_sym",+    "bq294701dsgr.kicad_mod",+    "bq294701dsgr.glb",+    "bq294701dsgr.step",+    "bq294701dsgr.lbr",+    "docs/hero.png",+    "docs/bq294701dsgr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "bq294701dsgr-hero.glb",+    "bq294701dsgr-hero.overlay.json"+  ],+  "component": {+    "mpn": "BQ294701DSGR",+    "manufacturer": "Texas Instruments",+    "package": "WSON-8-EP(2x2)",+    "pin_count": 9,+    "category": "Power Management (PMIC)",+    "subcategory": "Battery Management",+    "datasheet": "https://www.ti.com/cn/lit/gpn/bq2947",+    "parts": {+      "symbol": "bq294701dsgr.kicad_sym",+      "footprint": "bq294701dsgr.kicad_mod",+      "model_3d": "bq294701dsgr-hero.glb",+      "model_3d_plain": "bq294701dsgr.glb",+      "model_3d_step": "bq294701dsgr-etched.step",+      "model_3d_step_plain": "bq294701dsgr.step",+      "lbr": "bq294701dsgr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2860387",+      "digikey": "296-34985-2-ND",+      "mouser": "595-BQ294701DSGR"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T02:39:52Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-34985-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-BQ294701DSGR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "VDD",+        "type": "power_in",+        "description": "Unregulated IC supply input, recommended 3 V to 20 V (VDD-VSS) with absolute maximum 30 V; a series resistor limits current and a capacitor to ground filters noise."+      },+      {+        "number": "2",+        "name": "V4",+        "type": "input",+        "description": "Sense input for the positive voltage of the fourth (top) cell in the stack, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input."+      },+      {+        "number": "3",+        "name": "V3",+        "type": "input",+        "description": "Sense input for the positive voltage of the third cell from the bottom, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input."+      },+      {+        "number": "4",+        "name": "V2",+        "type": "input",+        "description": "Sense input for the positive voltage of the second cell from the bottom, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input."+      },+      {+        "number": "5",+        "name": "V1",+        "type": "input",+        "description": "Sense input for the positive voltage of the bottom cell in the stack, with recommended input range 0 V to 5 V and absolute maximum of 30 V; requires a series RC filter at the input."+      },+      {+        "number": "6",+        "name": "VSS",+        "type": "power_in",+        "description": "IC ground, connected to the negative terminal of the bottom cell; absolute maximum rating −0.3 V to 30 V relative to VSS for the other pins."+      },+      {+        "number": "7",+        "name": "CD",+        "type": "output",+        "description": "External delay capacitor connection that sets the overvoltage delay tCD = K × CCD (K = 10 to 20 s/µF, so 0.1 µF gives 1 s to 2 s); shorting CD to VSS enables the customer test mode with delay of 170 ms maximum."+      },+      {+        "number": "8",+        "name": "OUT",+        "type": "output",+        "description": "Overvoltage fault signal output, factory-set as CMOS active-high or open-drain active-low; the open-drain version requires an external pull-up resistor and absolute maximum is 30 V to VSS."+      },+      {+        "number": "9",+        "name": "PowerPAD",+        "type": "power_in",+        "description": "Exposed thermal pad that TI recommends connecting to VSS on the PCB and that must be soldered to the board for thermal and mechanical performance."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The datasheet pin table (page 4) lists the exposed thermal pad only as 'PowerPAD' with no number. Pi; The datasheet classifies CD as analog output (OA), but functionally it is the external timing-capaci; The 'description' fields combine the pin-table text with limits stated elsewhere in the datasheet (s"+        ],+        "pages_sent": 30,+        "cost_usd": 0.121,+        "at": "2026-10-08T02:39:35"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/bq2947",+        "pages": 30,+        "sha256": "0bb66de94396f561",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 9,+        "described": 9,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "bq294701dsgr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          2,+          1.98,+          0.82+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "7672cac8d88d8679800ef3bf90954e7996ea74e8ddb1f157f2d82bca6b2015e4",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "bq294701dsgr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          2,+          1.98,+          0.82+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "737c5a274200f65a0424e4c8fb83bee770ea8e1d85f3511c1fa1964cb8ad6936",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file