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BQ29311PWR

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Texas Instruments Battery Management ICs, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipbq29311pwrfactory-2.0.0extractor-text

Verified BQ29311PWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: BQ29311PWR · TSSOP-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C2862866, digikey BQ29311PWR-ND, mouser 595-BQ29311PWR
  • ✓family: TSSOP-24_4.4x7.8mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ox7bc0hk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.22)
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ bq29311pwr.kicad_sym✓ bq29311pwr.kicad_mod✓ bq29311pwr.step
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Ray Publish 0.1.0 d7f2f91 11d ago

BQ29311PWR

Texas Instruments · Battery Management ICs · TSSOP-24

BQ29311PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Diode protected BAT+ terminal and primary power source.
2 VBAT power_in Battery positive terminal sense input for regulator shutdown, with recommended range 0 V to VCC.
3 VC1 input Sense voltage input and balance current input for the most positive cell; connected to VC2 in 3-cell applications.
4 VC2 input Sense voltage input for the second most positive cell, balance current input for that cell, and return balance current for the most positive cell.
5 VC3 input Sense voltage input for the third most positive cell, balance current input for that cell, and return balance current for the second most positive cell.
6 VC4 input Sense voltage input for the least positive cell, balance current input for that cell, and return balance current for the third most positive cell.
7 VC5 input Sense voltage input for the most negative cell and return balance current for the least positive cell.
8 SR1 input Current sense positive terminal when charging, relative to SR2.
9 SR2 input Current sense positive terminal when discharging, relative to SR1.
10 CNTL input Active low input that enables CHG, DSG and PCHG, with an internal pullup.
11 GND power_in Analog ground pin and negative pack terminal.
12 VCELL output Output of the scaled value of the measured cell voltage, with absolute maximum of 7 V.
13 GND power_in Analog ground pin and negative pack terminal.
14 SCLK bidirectional Open-drain bidirectional serial interface clock with internal 10-kΩ pullup to VREG.
15 SDATA bidirectional Open-drain bidirectional serial interface data with internal 10-kΩ pullup to VREG.
16 CLKIN input Digital input that provides an alternate clock, with internal 100-kΩ pullup to VREG.
17 XALERT output Open-drain output used to indicate status register changes, with internal 100-kΩ pullup to VREG.
18 TOUT output Provides thermistor bias current.
19 VREG power_out Integrated 3.3-V regulator output, requiring an external 1-µF VREG capacitor.
20 LEDOUT output Provides current to drive the LED capacity display.
21 CHG output Push-pull output charge FET gate voltage supply.
22 PCHG output Push-pull output precharge FET gate voltage supply.
23 DSG output Push-pull output discharge FET gate voltage supply.
24 VPACK power_in Pack positive terminal and alternate power source.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Power Supply Chip
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC, VPACK -0.3 34 V 2
Supply voltage range VC1-VC4, VBAT VC1, VC2, VC3, VC4, VBAT -0.3 34 V 2
Voltage range VC5, SR1, SR2 VC5, SR1, SR2 -1 1 V 2
Input voltage range VC1 to VC2 through VC4 to VC5 -0.3 8.5 V 2
Input voltage range CLK-IN, SCLK, SDATA -0.3 7 V 2
Input voltage range CNTL -0.3 34 V 2
Output voltage range DSG, CHG, PCHG -0.3 V 2
Output voltage range LEDOUT, TOUT, SCLK, SDATA, VCELL, XALERT -0.3 7 V 2
Current for cell balancing 10 mA 2
ESD rating HBM 1.5 kV 2
ESD rating CDM 250 V 2
ESD rating MM 50 V 2
Operating free-air temperature range TA -25 85 °C 2
Storage temperature range Tstg -65 150 °C 2
Lead temperature (soldering) 260 °C 10 s soldering 2
Package power rating PW, TA ≤ 25°C 874 mW TA ≤ 25°C 2
Package power rating PW, TA = 70°C 559 mW TA = 70°C 2
Package power rating PW, TA = 85°C 454 mW TA = 85°C 2
Supply voltage (VCC or VPACK) VCC or VPACK 25 V 2
Battery input voltage VBAT VBAT 0 V 2
Cell input voltage VC1-VC4 VC1, VC2, VC3, VC4 0 V 2
Input voltage range SR1, SR2, VC5 VI -0.5 0.5 V 2
Cell differential voltage VCn-VC(n+1) VCn−VC(n+1) 0 5 V n = 1, 2, 3, 4 2
Output current XALERT IO 200 µA XALERT 2
Output current SDATA IO 50 µA SDATA 2
Output current VCELL IO -10 10 µA VCELL 2
Input current CNTL II -0.5 1 µA CNTL 2
Operating ambient temperature range TA -25 85 °C 2
Supply current 1 (TA = 25°C) I(CC1) 140 190 µA No load at VREG, TOUT, LEDOUT, XALERT, SCLK; TA = 25°C 3
Supply current 1 (TA = -25°C to 85°C) I(CC1) 220 µA CLKIN not used; TA = −25°C to 85°C 3
Supply current 2 I(CC2) 1 µA VBAT ≤ VSD, VPACK = 0; DSG, CHG and PCHG = off; TA = −25°C to 85°C 3
Regulator output voltage V(REG) 3.135 3.3 3.465 V IO ≤ 25 mA, TA = −25°C to 85°C 3
Regulator output change with temperature (TA = -25°C to 25°C) ∆V(REGTEMP) -1.74 0.2 1.74 % V(SD) = 6.5 V ≤ VCC ≤ 25 V, TA = −25°C to 25°C 3
Line regulation ∆V(REGLINE) 6 20 mV V(SD) = 6.5 V ≤ VCC ≤ 25 V, IO = 25 mA 3
Load regulation ∆V(REGLOAD) 2 20 mV 0.1 mA ≤ IO ≤ 25 mA, VCC = 14 V 3
VREG shutdown threshold range V(SD) 6.475 10.975 V Measured at VBAT 3
Accuracy of the shutdown threshold -5 5 % 3
Brownout threshold range VBO 7.975 12.475 V Measured at VBAT 3
Brownout threshold accuracy -5 5 % 3
Differential input voltage range V(CELL_IN) 0 4.5 V VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to VC5 3
VCELL scale factor K 0.144 0.15 0.156 3
OC detection threshold range, charge (overcurrent) V(OCD) 50 205 mV Charge (overcurrent) 4
OC detection threshold range, discharge (overload) V(OCD) -50 -205 mV Discharge (overload) 4
SC detection threshold range, charge V(SC) 100 475 mV Charge 4
SC detection threshold range, discharge V(SC) -100 -475 mV Discharge 4
OC detection threshold accuracy at V(OCD) = 50 mV (min) V(OCD_acr) 37.5 50 62.5 mV Charge and discharge; V(OCD) = 50 mV (min) 4
OC detection threshold accuracy at V(OCD) = 100 mV V(OCD_acr) 85 100 115 mV Charge and discharge; V(OCD) = 100 mV 4
OC detection threshold accuracy at V(OCD) = 205 mV (max) V(OCD_acr) 174 205 236 mV Charge and discharge; V(OCD) = 205 mV (max) 4
SC detection threshold accuracy at V(SC) = 100 mV (min) V(SC_acr) 75 100 125 mV Charge and discharge; V(SC) = 100 mV (min) 4
SC detection threshold accuracy at V(SC) = 200 mV V(SC_acr) 170 200 230 mV Charge and discharge; V(SC) = 200 mV 4
SC detection threshold accuracy at V(SC) = 475 mV (max) V(SC_acr) 403 475 547 mV Charge and discharge; V(SC) = 475 mV (max) 4
Output voltage DSG V(FETOL) 1 5 7 V VBAT = 16 V 4
Output voltage CHG V(FETOL) 1 5 7 V VPACK = 16 V 4
Output voltage PCHG V(FETOL) 8.5 10.5 11.5 V VPACK = 16 V 4
Output clamp voltage PCHG V(FETCLAMP) 3.3 3.5 3.7 V VPACK = 4.5 V 4
LEDOUT output voltage V(LEDOUT) 2.9 3.15 3.46 V IO = −25 mA at LEDOUT pin; TA = −25°C to 85°C 4
Internal pullup resistance XALERT, CLKIN R(PUP) 60 100 140 kΩ 4
Internal pullup resistance SDATA, SCLK R(PUP) 6 10 14 kΩ TA = −25°C to 85°C 4
CLKIN input frequency f(CLKIN) 32.1 32.768 33.42 kHz External clock 5
Power derating factor above TA = 25°C, PW 6.99 W/°C above TA = 25°C 2

CAD (KiCad official)

  • Symbol: BQ29311PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: bq29311pwr-etched.step / bq29311pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq29311pwr.step / bq29311pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 e8f9fa6552bc3101, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF