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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

BQ25896RTWR

Texas Instruments · Battery Management · QFN-24-EP(4x4)

BQ25896RTWR from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUS	power_in	Charger input voltage from 3.9 V to 14 V with integrated reverse blocking MOSFET; place 1 µF ceramic capacitor from VBUS to PGND as close as possible to IC.
2	PSEL	input	Power source selection input; high indicates USB host source with 500 mA default limit, low indicates adapter source with 3.25 A default limit.
3	PG	output	Open-drain active-low power good indicator; output low when VBUS is within 3.9 V to 14 V operating range above sleep threshold.
4	STAT	output	Open-drain charge status output; low during charge in progress, high when charge complete or disabled, blinks at 1 Hz when fault occurs.
5	SCL	input	I2C clock input; connect to logic rail via 10 kΩ pull-up resistor; supports up to 400 kHz fast mode operation.
6	SDA	bidirectional	I2C bidirectional data line; connect to logic rail via 10 kΩ pull-up resistor; slave address is 6BH with R/W bit.
7	INT	output	Open-drain interrupt output; sends active-low 256 µs pulse to host for status and fault reporting; connect via 10 kΩ pull-up resistor.
8	OTG	input	Boost mode enable input; activates USB OTG step-up converter to supply 4.55 V to 5.55 V adjustable output with maximum 2 A current.
9	CE	input	Active-low charge enable input; battery charging enabled when CHG_CONFIG = 1 and CE pin is low; pin must be actively pulled high or low.
10	ILIM	input	Analog input current limit control; sets maximum input current by regulating ILIM voltage at 0.8 V via external resistor or monitors proportional input current.
11	TS	input	Analog temperature sensor input; connect NTC thermistor (103AT recommended) for JEITA battery monitoring; suspends charging when temperature outside programmed thresholds.
12	QON	input	BATFET enable and reset control input; 1 sec low pulse exits shipping mode; 18 sec low pulse without VBUS triggers full system power reset; internal pull-up.
13	BAT	power_in	Positive battery terminal connection point operating 2.5 V to 4.6 V; integrated BATFET connects to SYS; requires 10 µF capacitor placed adjacent to pin.
14	BAT	power_in	Positive battery terminal connection point operating 2.5 V to 4.6 V; integrated BATFET connects to SYS; requires 10 µF capacitor placed adjacent to pin.
15	SYS	power_out	System power output regulated above minimum system voltage (default 3.5 V) from battery or buck converter; requires 20 µF output capacitor placed close to IC.
16	SYS	power_out	System power output regulated above minimum system voltage (default 3.5 V) from battery or buck converter; requires 20 µF output capacitor placed close to IC.
17	PGND	power_in	Power ground connection for high-current converter path; internally connected to LSFET source; connect directly to input/output capacitor grounds and single-point connection to analog ground.
18	PGND	power_in	Power ground connection for high-current converter path; internally connected to LSFET source; connect directly to input/output capacitor grounds and single-point connection to analog ground.
19	SW	passive	Switching node for buck converter LC output filter; internally connected to HSFET source and LSFET drain; requires 0.047 µF bootstrap capacitor to BTST.
20	SW	passive	Switching node for buck converter LC output filter; internally connected to HSFET source and LSFET drain; requires 0.047 µF bootstrap capacitor to BTST.
21	BTST	passive	Bootstrap supply node for high-side FET gate driver connected to bootstrap diode anode; requires 0.047 µF bootstrap capacitor between SW and BTST.
22	REGN	power_out	LDO output approximately 5 V for PWM gate drivers and TS pin bias with 50 mA current limit; requires 4.7 µF (≥10 V rating) ceramic capacitor to ground.
23	PMID	output	Intermediate power node connected to RBFET drain and HSFET drain; requires 1 µF capacitor to PGND with remaining input capacitance on PMID node.
24	NC	unconnected	No connection pin; should not be connected to any circuit signal or ground plane.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

CAD (KiCad official)

Symbol: BQ25896RTWR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq25896rtwr-etched.step / bq25896rtwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25896rtwr.step / bq25896rtwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (65 pp, sha256 0daf169500794ae6, retrieved 2026-09-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF