BQ25895RTWT

Texas Instruments · Battery Management · WQFN-24-EP(4x4)

BQ25895RTWT from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUS	power_in	Charger input voltage (recommended 3.9 V to 14 V, absolute maximum -2 V to 22 V with converter not switching); the internal RBFET connects VBUS to PMID, and a 1-µF ceramic capacitor should be placed from VBUS to PGND as close to the IC as possible.
2	D+	bidirectional	Positive line of the USB data pair used for D+/D- host and charging port detection (DCD, BC1.2 primary and secondary detection) and the MaxCharge adjustable high-voltage adapter handshake, with an absolute maximum of -0.3 V to 7 V.
3	D-	bidirectional	Negative line of the USB data pair used for D+/D- host and charging port detection (DCD, BC1.2 primary and secondary detection) and the MaxCharge adjustable high-voltage adapter handshake, with an absolute maximum of -0.3 V to 7 V.
4	STAT	output	Open-drain charge status output that is LOW during charge in progress, HIGH on charge complete or charge disabled, blinks at 1 Hz on fault, and should be connected to a pull-up rail through 10 kΩ (absolute maximum 20 V, sink current 6 mA).
5	SCL	input	I2C interface clock input that should be connected to the logic rail through a 10-kΩ resistor (absolute maximum -0.3 V to 7 V).
6	SDA	bidirectional	I2C interface data line that should be connected to the logic rail through a 10-kΩ resistor (absolute maximum -0.3 V to 7 V).
7	INT	output	Open-drain interrupt output that sends an active-low 256-µs pulse to the host to report charger status and faults, and should be pulled up to a logic rail through 10 kΩ (sink current 6 mA maximum).
8	OTG	input	Boost mode enable input; boost mode is activated when OTG_CONFIG = 1, OTG is high, and no input source is detected at VBUS (absolute maximum 7 V).
9	CE	input	Active-low charge enable input; battery charging is enabled when CHG_CONFIG = 1 and CE is low, and CE must be pulled either high or low rather than left floating.
10	ILIM	input	Input current limit pin that sets the maximum input current by regulating ILIM at 0.8 V with IINMAX = KILIM/RILIM, can also monitor input current when ILIM is below 0.8 V, and does not support limits below 500 mA (absolute maximum 5 V).
11	TS	input	Temperature qualification input for a negative temperature coefficient thermistor (103AT-2 recommended), biased from REGN through a resistor divider, with charge suspended when TS is out of range (absolute maximum 7 V).
12	QON	input	BATFET enable/reset control input with an internal pull-up; a logic low of tSHIPMODE exits shipping mode, and a logic low of tQON_RST resets SYS when VBUS is not plugged in (absolute maximum 7 V).
13	BAT	power_in	Battery connection to the positive terminal of the battery pack, with the internal BATFET connected between BAT and SYS; a 10-µF capacitor should be placed close to the BAT pin (absolute maximum 6 V with converter not switching).
14	BAT	power_in	Battery connection to the positive terminal of the battery pack, with the internal BATFET connected between BAT and SYS; a 10-µF capacitor should be placed close to the BAT pin (absolute maximum 6 V with converter not switching).
15	SYS	power_out	System connection point where the switch-mode converter keeps SYS above the minimum system voltage (default 3.5 V) when the battery is low; a 20-µF capacitor should be placed close to the SYS pin.
16	SYS	power_out	System connection point where the switch-mode converter keeps SYS above the minimum system voltage (default 3.5 V) when the battery is low; a 20-µF capacitor should be placed close to the SYS pin.
17	PGND	power_in	Power ground for the high-current converter, connected to the source of the LSFET, with a single-point connection to analog GND near the IC PGND pin recommended.
18	PGND	power_in	Power ground for the high-current converter, connected to the source of the LSFET, with a single-point connection to analog GND near the IC PGND pin recommended.
19	SW	output	Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor connected from SW to BTST (absolute maximum -2 V to 16 V, with -3 V to 16 V peak for 10 ns).
20	SW	output	Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor connected from SW to BTST (absolute maximum -2 V to 16 V, with -3 V to 16 V peak for 10 ns).
21	BTST	power_out	Positive supply for the PWM high-side driver, connected to the anode of the bootstrap diode, with a 0.047-µF bootstrap capacitor from SW to BTST (absolute maximum -0.3 V to 20 V).
22	REGN	power_out	PWM low-side driver positive supply output connected to the bootstrap diode cathode, requiring a 4.7-µF (10 V rated) ceramic capacitor to analog GND placed close to the IC, which also biases the TS pin.
23	PMID	power_out	Battery boost mode output connected to the RBFET and HSFET drains, requiring at least 8.2 µF to PGND without OTG, or 40 µF for up to 2.4 A and 60 µF for up to 3.1 A output with OTG.
24	DSEL	output	Open-drain D+/D- multiplexer selection control, pulled up to a logic rail through 10 kΩ, which is driven low during D+/D- detection and when MaxCharge is detected and floats high for other input source types (absolute maximum 20 V, sink current 6 mA).
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VBUS voltage range (converter not switching)	VBUS	-2		22	V	converter not switching	6
PMID voltage range (converter not switching)	PMID	-0.3		22	V	converter not switching	6
STAT voltage range	STAT	-0.3		20	V		6
DSEL voltage range	DSEL	-0.3		20	V		6
BTST voltage range	BTST	-0.3		20	V		6
SW voltage range	SW	-2		16	V		6
SW voltage peak	SW	-3		16	V	peak for 10 ns duration	6
BAT, SYS voltage range	BAT, SYS	-0.3		6	V	converter not switching	6
SDA, SCL, INT, OTG, REGN, TS, CE, QON voltage range		-0.3		7	V		6
D+, D- voltage range	D+, D-	-0.3		7	V		6
BTST to SW voltage range	BTST to SW	-0.3		7	V		6
PGND to GND voltage range	PGND to GND	-0.3		0.3	V		6
ILIM voltage range	ILIM	-0.3		5	V		6
Output sink current INT, STAT				6	mA		6
Output sink current DSEL				6	mA		6
Junction temperature	TJ	-40		150	°C		6
Storage temperature range	Tstg	-65		150	°C		6
Input voltage	VIN	3.9		14	V		6
Input current (VBUS)	IIN			3.25	A		6
Output current (SW)	ISYS			5	A		6
Battery voltage	VBAT			4.608	V		6
Fast charging current	IBAT			5	A		6
Discharging current with internal MOSFET (continuous)	IBAT			6	A	continuous	6
Discharging current with internal MOSFET (peak)	IBAT			9	A	up to 1 sec duration	6
Operating free-air temperature range	TA	-40		85	°C		7
Input high-impedance quiescent current, BATFET disabled	I(VBUS_HIZ)		12	23	µA	High-Z mode, no VBUS, BATFET disabled (REG09[5]=1), battery monitor disabled, TJ < 85°C	7
Input high-impedance quiescent current, BATFET enabled	IBAT		32	60	µA	High-Z mode, no VBUS, BATFET enabled (REG09[5]=0), battery monitor disabled, TJ < 85°C	7
Input supply current (VBUS) in High-Z mode	I(VBUS_HIZ)		15	35	µA	V(VBUS)= 5 V, High-Z mode, no battery, battery monitor disabled	7
Input supply current (VBUS) in buck mode	I(VBUS)		1.5	3	mA	VBUS > V(UVLO), VBUS > VBAT, converter not switching	7
VBUS operating range	V(VBUS_OP)	3.9		14	V		7
Sleep mode falling threshold	V(SLEEP)	25	65	120	mV		7
Sleep mode rising threshold	V(SLEEPZ)	130	250	370	mV		7
Typical system regulation voltage minimum DC system output	VSYS(MIN)	3.5	3.65		V	VBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1]=101), ISYS= 0 A	8
Maximum DC system voltage output	VSYS(MAX)	4.4	4.42		V	VBAT = 4.35 V, SYS_MIN = 3.5V (REG03[3:1]=101), ISYS= 0 A	8
Top reverse blocking MOSFET (RBFET) on-resistance, VBUS to PMID	RON(RBFET)	27		38	mΩ	TJ = -40°C to +85°C	8
Top switching MOSFET (HSFET) on-resistance, PMID to SW	RON(HSFET)	27		39	mΩ	TJ = -40°C to +85°C	8
Bottom switching MOSFET (LSFET) on-resistance, SW to GND	RON(LSFET)	16		24	mΩ	TJ = -40°C to +85°C	8
SYS-BAT MOSFET (BATFET) on-resistance	RON(BATFET)	11		13	mΩ	TJ = 25°C	8
Battery good comparator rising threshold	VBAT(GD)	3.4	3.55	3.7	V	VBAT rising	8
Typical charge voltage range	VBAT(REG_RANGE)	3.84		4.608	V		8
Charge voltage resolution accuracy	VBAT(REG)	-0.5		0.5	%	VBAT = 4.208 V (REG06[7:2]=010111) or VBAT = 4.352 V (REG06[7:2]=100000), TJ = -40°C to +85°C	8
Typical fast charge current regulation range	I(CHG_REG_RANGE)	0		5056	mA		8
Fast charge current regulation accuracy	I(CHG_REG_ACC)	-20		20	%	VBAT = 3.1 V or 3.8 V, ICHG = 128 mA, TJ = -40°C to +85°C	8
Fast charge current regulation accuracy	I(CHG_REG_ACC)	-5		5	%	VBAT = 3.1 V or 3.8 V, ICHG=1792 mA, TJ = -40°C to +85°C	8
Battery LOWV falling threshold	VBAT(LOWV)	2.6	2.8	2.9	V	Fast charge to precharge, BATLOWV (REG06[1]) = 1	8
Termination current accuracy	I(TERM_ACC)	-20		20	%	ITERM = 256 mA, ICHG> 1344 mA, TJ = -20°C to +85°C	8
Typical input voltage regulation range	VIN(DPM_RANGE)	3.9		15.3	V		9
Typical input current regulation range	IIN(DPM_RANGE)	100		3250	mA		9
Input current regulation accuracy, adapter 1.5 A	IIN(DPM_ACC)	1300	1400	1500	mA	VBAT = 5 V, current pulled from SW, Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA	9
Input voltage regulation accuracy	VIN(DPM_ACC)	-3		3	%	VINDPM = 4.4 V, 9 V	9
PWM switching frequency, oscillator frequency	FSW	1.32	1.68		MHz		9
Typical boost mode regulation voltage range	V(OTG_REG_RANGE)	4.55		5.55	V		9
REGN LDO output voltage	V(REGN)	5.6	6	6.4	V	V(VBUS) = 9 V, I(REGN) = 40 mA	9
Cold temperature threshold, TS pin voltage rising threshold	V(LTF)	72.75	73.25	73.75	%	As percentage to V(REGN)	9
Hot temperature TS pin voltage rising threshold	V(HTF)	47.75	48.25	48.75	%	As percentage to V(REGN)	9
Junction-to-ambient thermal resistance	RθJA		31.8		°C/W		7
Junction-to-case (top) thermal resistance	RθJC((op)		27.9		°C/W		7
Junction-to-board thermal resistance	RθJB		8.7		°C/W		7
Junction-to-top characterization parameter	ψJT		0.3		°C/W		7
Junction-to-board characterization parameter	ψJB		8.7		°C/W		7
Junction-to-case (bottom) thermal resistance	RθJC(bot)		2		°C/W		7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper	55

CAD (KiCad official)

Symbol: BQ25895RTWT
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq25895rtwt-etched.step / bq25895rtwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25895rtwt.step / bq25895rtwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (65 pp, sha256 9e00f1f30064dad8, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# BQ25895RTWT

**Texas Instruments** · Battery Management · WQFN-24-EP(4x4)

BQ25895RTWT from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS | power_in | Charger input voltage (recommended 3.9 V to 14 V, absolute maximum -2 V to 22 V with converter not switching); the internal RBFET connects VBUS to PMID, and a 1-µF ceramic capacitor should be placed from VBUS to PGND as close to the IC as possible. |
| 2 | D+ | bidirectional | Positive line of the USB data pair used for D+/D- host and charging port detection (DCD, BC1.2 primary and secondary detection) and the MaxCharge adjustable high-voltage adapter handshake, with an absolute maximum of -0.3 V to 7 V. |
| 3 | D- | bidirectional | Negative line of the USB data pair used for D+/D- host and charging port detection (DCD, BC1.2 primary and secondary detection) and the MaxCharge adjustable high-voltage adapter handshake, with an absolute maximum of -0.3 V to 7 V. |
| 4 | STAT | output | Open-drain charge status output that is LOW during charge in progress, HIGH on charge complete or charge disabled, blinks at 1 Hz on fault, and should be connected to a pull-up rail through 10 kΩ (absolute maximum 20 V, sink current 6 mA). |
| 5 | SCL | input | I2C interface clock input that should be connected to the logic rail through a 10-kΩ resistor (absolute maximum -0.3 V to 7 V). |
| 6 | SDA | bidirectional | I2C interface data line that should be connected to the logic rail through a 10-kΩ resistor (absolute maximum -0.3 V to 7 V). |
| 7 | INT | output | Open-drain interrupt output that sends an active-low 256-µs pulse to the host to report charger status and faults, and should be pulled up to a logic rail through 10 kΩ (sink current 6 mA maximum). |
| 8 | OTG | input | Boost mode enable input; boost mode is activated when OTG_CONFIG = 1, OTG is high, and no input source is detected at VBUS (absolute maximum 7 V). |
| 9 | CE | input | Active-low charge enable input; battery charging is enabled when CHG_CONFIG = 1 and CE is low, and CE must be pulled either high or low rather than left floating. |
| 10 | ILIM | input | Input current limit pin that sets the maximum input current by regulating ILIM at 0.8 V with IINMAX = KILIM/RILIM, can also monitor input current when ILIM is below 0.8 V, and does not support limits below 500 mA (absolute maximum 5 V). |
| 11 | TS | input | Temperature qualification input for a negative temperature coefficient thermistor (103AT-2 recommended), biased from REGN through a resistor divider, with charge suspended when TS is out of range (absolute maximum 7 V). |
| 12 | QON | input | BATFET enable/reset control input with an internal pull-up; a logic low of tSHIPMODE exits shipping mode, and a logic low of tQON_RST resets SYS when VBUS is not plugged in (absolute maximum 7 V). |
| 13 | BAT | power_in | Battery connection to the positive terminal of the battery pack, with the internal BATFET connected between BAT and SYS; a 10-µF capacitor should be placed close to the BAT pin (absolute maximum 6 V with converter not switching). |
| 14 | BAT | power_in | Battery connection to the positive terminal of the battery pack, with the internal BATFET connected between BAT and SYS; a 10-µF capacitor should be placed close to the BAT pin (absolute maximum 6 V with converter not switching). |
| 15 | SYS | power_out | System connection point where the switch-mode converter keeps SYS above the minimum system voltage (default 3.5 V) when the battery is low; a 20-µF capacitor should be placed close to the SYS pin. |
| 16 | SYS | power_out | System connection point where the switch-mode converter keeps SYS above the minimum system voltage (default 3.5 V) when the battery is low; a 20-µF capacitor should be placed close to the SYS pin. |
| 17 | PGND | power_in | Power ground for the high-current converter, connected to the source of the LSFET, with a single-point connection to analog GND near the IC PGND pin recommended. |
| 18 | PGND | power_in | Power ground for the high-current converter, connected to the source of the LSFET, with a single-point connection to analog GND near the IC PGND pin recommended. |
| 19 | SW | output | Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor connected from SW to BTST (absolute maximum -2 V to 16 V, with -3 V to 16 V peak for 10 ns). |
| 20 | SW | output | Switching node connecting to the output inductor, with a 0.047-µF bootstrap capacitor connected from SW to BTST (absolute maximum -2 V to 16 V, with -3 V to 16 V peak for 10 ns). |
| 21 | BTST | power_out | Positive supply for the PWM high-side driver, connected to the anode of the bootstrap diode, with a 0.047-µF bootstrap capacitor from SW to BTST (absolute maximum -0.3 V to 20 V). |
| 22 | REGN | power_out | PWM low-side driver positive supply output connected to the bootstrap diode cathode, requiring a 4.7-µF (10 V rated) ceramic capacitor to analog GND placed close to the IC, which also biases the TS pin. |
| 23 | PMID | power_out | Battery boost mode output connected to the RBFET and HSFET drains, requiring at least 8.2 µF to PGND without OTG, or 40 µF for up to 2.4 A and 60 µF for up to 3.1 A output with OTG. |
| 24 | DSEL | output | Open-drain D+/D- multiplexer selection control, pulled up to a logic rail through 10 kΩ, which is driven low during D+/D- detection and when MaxCharge is detected and floats high for other input source types (absolute maximum 20 V, sink current 6 mA). |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBUS voltage range (converter not switching) | VBUS | -2 |  | 22 | V | converter not switching | 6 |
| PMID voltage range (converter not switching) | PMID | -0.3 |  | 22 | V | converter not switching | 6 |
| STAT voltage range | STAT | -0.3 |  | 20 | V |  | 6 |
| DSEL voltage range | DSEL | -0.3 |  | 20 | V |  | 6 |
| BTST voltage range | BTST | -0.3 |  | 20 | V |  | 6 |
| SW voltage range | SW | -2 |  | 16 | V |  | 6 |
| SW voltage peak | SW | -3 |  | 16 | V | peak for 10 ns duration | 6 |
| BAT, SYS voltage range | BAT, SYS | -0.3 |  | 6 | V | converter not switching | 6 |
| SDA, SCL, INT, OTG, REGN, TS, CE, QON voltage range |  | -0.3 |  | 7 | V |  | 6 |
| D+, D- voltage range | D+, D- | -0.3 |  | 7 | V |  | 6 |
| BTST to SW voltage range | BTST to SW | -0.3 |  | 7 | V |  | 6 |
| PGND to GND voltage range | PGND to GND | -0.3 |  | 0.3 | V |  | 6 |
| ILIM voltage range | ILIM | -0.3 |  | 5 | V |  | 6 |
| Output sink current INT, STAT |  |  |  | 6 | mA |  | 6 |
| Output sink current DSEL |  |  |  | 6 | mA |  | 6 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 6 |
| Input voltage | VIN | 3.9 |  | 14 | V |  | 6 |
| Input current (VBUS) | IIN |  |  | 3.25 | A |  | 6 |
| Output current (SW) | ISYS |  |  | 5 | A |  | 6 |
| Battery voltage | VBAT |  |  | 4.608 | V |  | 6 |
| Fast charging current | IBAT |  |  | 5 | A |  | 6 |
| Discharging current with internal MOSFET (continuous) | IBAT |  |  | 6 | A | continuous | 6 |
| Discharging current with internal MOSFET (peak) | IBAT |  |  | 9 | A | up to 1 sec duration | 6 |
| Operating free-air temperature range | TA | -40 |  | 85 | °C |  | 7 |
| Input high-impedance quiescent current, BATFET disabled | I(VBUS_HIZ) |  | 12 | 23 | µA | High-Z mode, no VBUS, BATFET disabled (REG09[5]=1), battery monitor disabled, TJ < 85°C | 7 |
| Input high-impedance quiescent current, BATFET enabled | IBAT |  | 32 | 60 | µA | High-Z mode, no VBUS, BATFET enabled (REG09[5]=0), battery monitor disabled, TJ < 85°C | 7 |
| Input supply current (VBUS) in High-Z mode | I(VBUS_HIZ) |  | 15 | 35 | µA | V(VBUS)= 5 V, High-Z mode, no battery, battery monitor disabled | 7 |
| Input supply current (VBUS) in buck mode | I(VBUS) |  | 1.5 | 3 | mA | VBUS > V(UVLO), VBUS > VBAT, converter not switching | 7 |
| VBUS operating range | V(VBUS_OP) | 3.9 |  | 14 | V |  | 7 |
| Sleep mode falling threshold | V(SLEEP) | 25 | 65 | 120 | mV |  | 7 |
| Sleep mode rising threshold | V(SLEEPZ) | 130 | 250 | 370 | mV |  | 7 |
| Typical system regulation voltage minimum DC system output | VSYS(MIN) | 3.5 | 3.65 |  | V | VBAT< VSYS(MIN), SYS_MIN = 3.5 V (REG03[3:1]=101), ISYS= 0 A | 8 |
| Maximum DC system voltage output | VSYS(MAX) | 4.4 | 4.42 |  | V | VBAT = 4.35 V, SYS_MIN = 3.5V (REG03[3:1]=101), ISYS= 0 A | 8 |
| Top reverse blocking MOSFET (RBFET) on-resistance, VBUS to PMID | RON(RBFET) | 27 |  | 38 | mΩ | TJ = -40°C to +85°C | 8 |
| Top switching MOSFET (HSFET) on-resistance, PMID to SW | RON(HSFET) | 27 |  | 39 | mΩ | TJ = -40°C to +85°C | 8 |
| Bottom switching MOSFET (LSFET) on-resistance, SW to GND | RON(LSFET) | 16 |  | 24 | mΩ | TJ = -40°C to +85°C | 8 |
| SYS-BAT MOSFET (BATFET) on-resistance | RON(BATFET) | 11 |  | 13 | mΩ | TJ = 25°C | 8 |
| Battery good comparator rising threshold | VBAT(GD) | 3.4 | 3.55 | 3.7 | V | VBAT rising | 8 |
| Typical charge voltage range | VBAT(REG_RANGE) | 3.84 |  | 4.608 | V |  | 8 |
| Charge voltage resolution accuracy | VBAT(REG) | -0.5 |  | 0.5 | % | VBAT = 4.208 V (REG06[7:2]=010111) or VBAT = 4.352 V (REG06[7:2]=100000), TJ = -40°C to +85°C | 8 |
| Typical fast charge current regulation range | I(CHG_REG_RANGE) | 0 |  | 5056 | mA |  | 8 |
| Fast charge current regulation accuracy | I(CHG_REG_ACC) | -20 |  | 20 | % | VBAT = 3.1 V or 3.8 V, ICHG = 128 mA, TJ = -40°C to +85°C | 8 |
| Fast charge current regulation accuracy | I(CHG_REG_ACC) | -5 |  | 5 | % | VBAT = 3.1 V or 3.8 V, ICHG=1792 mA, TJ = -40°C to +85°C | 8 |
| Battery LOWV falling threshold | VBAT(LOWV) | 2.6 | 2.8 | 2.9 | V | Fast charge to precharge, BATLOWV (REG06[1]) = 1 | 8 |
| Termination current accuracy | I(TERM_ACC) | -20 |  | 20 | % | ITERM = 256 mA, ICHG> 1344 mA, TJ = -20°C to +85°C | 8 |
| Typical input voltage regulation range | VIN(DPM_RANGE) | 3.9 |  | 15.3 | V |  | 9 |
| Typical input current regulation range | IIN(DPM_RANGE) | 100 |  | 3250 | mA |  | 9 |
| Input current regulation accuracy, adapter 1.5 A | IIN(DPM_ACC) | 1300 | 1400 | 1500 | mA | VBAT = 5 V, current pulled from SW, Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA | 9 |
| Input voltage regulation accuracy | VIN(DPM_ACC) | -3 |  | 3 | % | VINDPM = 4.4 V, 9 V | 9 |
| PWM switching frequency, oscillator frequency | FSW | 1.32 | 1.68 |  | MHz |  | 9 |
| Typical boost mode regulation voltage range | V(OTG_REG_RANGE) | 4.55 |  | 5.55 | V |  | 9 |
| REGN LDO output voltage | V(REGN) | 5.6 | 6 | 6.4 | V | V(VBUS) = 9 V, I(REGN) = 40 mA | 9 |
| Cold temperature threshold, TS pin voltage rising threshold | V(LTF) | 72.75 | 73.25 | 73.75 | % | As percentage to V(REGN) | 9 |
| Hot temperature TS pin voltage rising threshold | V(HTF) | 47.75 | 48.25 | 48.75 | % | As percentage to V(REGN) | 9 |
| Junction-to-ambient thermal resistance | RθJA |  | 31.8 |  | °C/W |  | 7 |
| Junction-to-case (top) thermal resistance | RθJC((op) |  | 27.9 |  | °C/W |  | 7 |
| Junction-to-board thermal resistance | RθJB |  | 8.7 |  | °C/W |  | 7 |
| Junction-to-top characterization parameter | ψJT |  | 0.3 |  | °C/W |  | 7 |
| Junction-to-board characterization parameter | ψJB |  | 8.7 |  | °C/W |  | 7 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2 |  | °C/W |  | 7 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper | 55 |

## CAD (KiCad official)

- Symbol: `BQ25895RTWT`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `bq25895rtwt-etched.step` / `bq25895rtwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq25895rtwt.step` / `bq25895rtwt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq25895) (65 pp, sha256 `9e00f1f30064dad8`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/bq25895rtwt-datasheet.pdf)