component
BQ25887RGER
Public Made by Adomby adom
Texas Instruments Battery Management ICs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownBQ25887RGER
Texas Instruments · Battery Management ICs · QFN-24-EP(4x4)
BQ25887RGER from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG | output | Open-drain active-low power good indicator, connect to pull-up rail via 10-kΩ resistor; LOW indicates a good input source within VVBUS_OP that can provide more than IPOORSRC (30 mA). |
| 2 | STAT | output | Open-drain charge status indicator, connect to pull-up rail via 10-kΩ resistor; LOW means charge in progress, HIGH means charge complete or disabled, blinks at 1 Hz on any fault, and can be disabled with the STAT_DIS bit. |
| 3 | CD | input | Active-high chip disable pin; pulling it high disables charge and places the device in HIZ mode (ADC and I2C still allowed), internally pulled low with a 900-kΩ resistor. |
| 4 | SDA | bidirectional | I2C interface data, connect to the pull-up rail through a 10-kΩ resistor. |
| 5 | SCL | input | I2C interface clock, connect to the pull-up rail through a 10-kΩ resistor. |
| 6 | INT | output | Open-drain active-low interrupt output, connect to pull-up rail via a 10-kΩ resistor; sends a 256-µs pulse to the host to report charger status and faults. |
| 7 | TS | input | Temperature qualification voltage input for a negative temperature coefficient thermistor (103AT-2 recommended), with the window programmed by a resistor divider from REGN to TS to GND; charge suspends when out of range. |
| 8 | ILIM | input | Input current limit pin regulated at 0.8 V, where a resistor to ground sets IINMAX = KILIM/RILIM (limits below 500 mA not supported) and the pin can monitor input current; pull to GND if unused and do not float. |
| 9 | MID | input | Voltage input for the midpoint between cells in 2S1P configuration, used for cell balancing and VMID ADC measurement; a 300-ohm series resistor to the cell midpoint is recommended for bottom-cell reverse-plug protection. |
| 10 | CBSET | power_in | Cell balancing power pin, connected to the midpoint between the two batteries through a current-limit resistor that sets the balancing current, which should not exceed 400 mA. |
| 11 | REGN | power_out | Gate drive supply and bias for the internal MOSFET drivers and IC, bypass to GND with a 4.7-µF ceramic capacitor; REGN current limit is 50 mA. |
| 12 | BTST | passive | PWM high-side driver supply connected internally to the bootstrap diode cathode; connect a 47-nF bootstrap capacitor from SW to BTST. |
| 13 | BAT | passive | Battery power connection; connect at least 10 µF of capacitance after derating close to the BAT pin and GND. |
| 14 | BAT | passive | Battery power connection; connect at least 10 µF of capacitance after derating close to the BAT pin and GND. |
| 15 | SNS | output | Sense output for charge current sensing; place a 44-µF ceramic capacitor on this pin for stability. |
| 16 | SNS | output | Sense output for charge current sensing; place a 44-µF ceramic capacitor on this pin for stability. |
| 17 | SW | passive | Inductor connection to the switched side of the external inductor. |
| 18 | SW | passive | Inductor connection to the switched side of the external inductor. |
| 19 | GND | power_in | Ground return. |
| 20 | GND | power_in | Ground return. |
| 21 | PMID | passive | Blocking MOSFET connection; minimum total low-ESR capacitance on VBUS and PMID after derating is 10 µF, with at least 1 µF at VBUS and the remainder at PMID. |
| 22 | PMID | passive | Blocking MOSFET connection; minimum total low-ESR capacitance on VBUS and PMID after derating is 10 µF, with at least 1 µF at VBUS and the remainder at PMID. |
| 23 | VBUS | power_in | Input supply connected to the external DC supply; bypass to GND with at least 1-µF ceramic capacitor placed as close to the IC as possible. |
| 24 | PSEL | input | Power source selection input; HIGH indicates USB host source (500 mA) and LOW indicates adapter source (3.0 A). |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-24-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBUS voltage (converter not switching) | VBUS | -0.3 | 20 | V | converter not switching | 6 | |
| PMID voltage | PMID | -0.3 | 8.5 | V | converter not switching | 6 | |
| BAT, SNS, MID, CBSET voltage | -0.3 | 12 | V | converter not switching | 6 | ||
| SW voltage | SW | -0.3 | 13 | V | -2V for 50ns | 6 | |
| BTST voltage | BTST | -0.3 | 19 | V | 6 | ||
| REGN, STAT, /PG, TS voltage | -0.3 | 6 | V | 6 | |||
| ILIM voltage | ILIM | -0.3 | 5 | V | 6 | ||
| BTST to SW voltage | -0.3 | 6 | V | 6 | |||
| SDA, SCL, /INT, CD, PSEL voltage | -0.3 | 6 | V | 6 | |||
| BAT to CBSET voltage | 0 | 12 | V | 6 | |||
| Output sink current /INT, STAT, /PG | 6 | mA | 6 | ||||
| Junction temperature | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 6 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 6 | |
| ESD CDM | V(ESD) | -250 | 250 | V | CDM per JESD22-C101 | 6 | |
| Input voltage | VVBUS | 3.9 | 6.2 | V | 6 | ||
| Average input current (VBUS) | IVBUS | 3.3 | A | 6 | |||
| Average charge current (IBAT) | IBAT | 2.2 | A | 6 | |||
| RMS discharging current with internal MOSFET | IBAT_RMS | 5 | A | 6 | |||
| Peak discharging current with internal MOSFET | IBAT_PK | 9 | A | up to 1us | 6 | ||
| Battery voltage | VBAT | 9.2 | V | 6 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RΘJA | 32.4 | °C/W | JEDEC, RGE VQFN 24-pin | 7 | ||
| Junction-to-case (top) thermal resistance | RΘJC(top) | 26.7 | °C/W | 7 | |||
| Junction-to-board thermal resistance | RΘJB | 10.7 | °C/W | 7 | |||
| Junction-to-top characterization parameter | ΨJT | 0.4 | °C/W | 7 | |||
| Junction-to-board characterization parameter | ΨJB | 10.6 | °C/W | 7 | |||
| Junction-to-case (bottom) thermal resistance | RΘJC(bot) | 3.7 | °C/W | 7 | |||
| Battery discharge current (BAT) | IBAT | 12 | 14 | µA | VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, TJ=25C, ADC Disabled | 7 | |
| Battery discharge current (BAT) | IBAT | 12 | 20 | µA | VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, TJ < 85C, ADC Disabled | 7 | |
| Input supply current in HIZ | IVBUS_HIZ | 30 | 38 | µA | VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, 25℃ | 7 | |
| Input supply current in HIZ | IVBUS_HIZ | 30 | 48 | µA | VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, <85℃ | 7 | |
| Input supply current (VBUS) | IVBUS | 1.5 | 3 | mA | VBUS = 5 V, VBAT = 7.6 V, converter not switching | 7 | |
| VBUS UVLO rising | VVBUS_UVLO_RISING | 3.3 | 3.68 | V | VBUS rising | 7 | |
| VBUS over-voltage rising threshold | VVBUS_OV | 6.2 | 6.6 | V | VBUS rising | 7 | |
| VBUS over-voltage falling threshold | VVBUS_OV | 5.9 | 6.4 | V | VBUS falling | 7 | |
| Battery for active I2C | VBAT_UVLO_RISING | 3.7 | 4 | 4.42 | V | VBAT rising | 7 |
| Charge voltage accuracy 4.20 V | VCELLREG_ACC | 4.179 | 4.2 | 4.221 | V | VREG = 4.20 V, TJ = 0°C to 85°C | 7 |
| Charge voltage accuracy 4.35 V | VCELLREG_ACC | 4.328 | 4.35 | 4.372 | V | VREG = 4.35 V, TJ = 0°C to 85°C | 7 |
| Fast charge current accuracy 1000 mA | ICHG_ACC | -7.5 | 7.5 | % | ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C | 7 | |
| Fast charge current accuracy 500 mA | ICHG_ACC | -15 | 15 | % | ICHG = 500mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C | 7 | |
| Fast charge current accuracy 250 mA | ICHG_ACC | -25 | 25 | % | ICHG = 250 mA, VBAT = 6.2 V or 7.6 V, TJ = 0°C to 85°C | 7 | |
| Precharge current accuracy | IPRECHG_ACC | 170 | 237 | mA | VBAT = 5.2 V, IPRECHG = 200 mA, TJ = 25°C | 8 | |
| Precharge current accuracy | IPRECHG_ACC | 150 | 245 | mA | VBAT = 5.2 V, IPRECHG = 200 mA, TJ = 0°C to 85°C | 8 | |
| Termination current accuracy 150 mA | ITERM_ACC | 143 | 157 | mA | ICHG = 1.5A, ITERM = 150 mA, TJ = 25°C | 8 | |
| Termination current accuracy 150 mA | ITERM_ACC | 120 | 180 | mA | ICHG = 1.5A, ITERM = 150 mA, TJ = 0°C to 85°C | 8 | |
| Termination current accuracy 50 mA | ITERM_ACC | 45 | 60 | mA | ICHG = 1.5A, ITERM = 50 mA, TJ = 25°C | 8 | |
| Termination current accuracy 50 mA | ITERM_ACC | 22 | 75 | mA | ICHG = 1.5A, ITERM = 50 mA, TJ = 0°C to 85°C | 8 | |
| Short battery voltage rising threshold | VCELL_SHORT_RISING | 2.05 | 2.2 | 2.35 | V | VCELL rising | 8 |
| Short battery voltage falling threshold | VCELL_SHORT_FALLING | 1.85 | 2 | 2.15 | V | VCELL falling | 8 |
| VCELL LOWV rising threshold | VCELL_LOWV_RISING | 2.65 | 2.8 | 2.95 | V | VCELL rising, VBATLOW = 2.8 V | 8 |
| High-side MOSFET on-resistance | RON_QHS | 32 | 35 | mΩ | TJ = 25°C | 8 | |
| High-side MOSFET on-resistance | RON_QHS | 32 | 47 | mΩ | TJ =, 40°C to 125°C | 8 | |
| Low-side MOSFET on-resistance | RON_QLS | 42 | 46 | mΩ | TJ = 25°C | 8 | |
| Low-side MOSFET on-resistance | RON_QLS | 42 | 63 | mΩ | TJ =, 40°C to 125°C | 8 | |
| BAT discharge current source | IBAT_DISCHG | 8 | 11.5 | 16 | mA | VBAT = 8V, EN_BAT_DISCHG = 1 | 8 |
| Input current regulation limit 500 mA | IINDPM_ACC | 438 | 469 | 500 | mA | IINDPM = 500 mA | 8 |
| Blocking MOSFET on-resistance | RON_QBLK | 33 | 51 | mΩ | TJ =, 40°C to 125°C | 8 | |
| PWM switching frequency | FSW | 1.35 | 1.5 | 1.65 | MHz | Oscillator frequency | 9 |
| REGN LDO output voltage | VREGN | 4.7 | 4.8 | 5.15 | V | VVBUS = 5 V, IREGN = 20 mA | 10 |
| Charge safety timer accuracy | tSAFETY | 10.8 | 12 | 13.2 | hr | CHG_TIMER = 12 hours | 11 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 1. Put SNS output capacitor as close to SNS and GND pins as possible. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. | 74 |
CAD (KiCad official)
- Symbol:
BQ25887RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
bq25887rger-etched.step/bq25887rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bq25887rger.step/bq25887rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (85 pp, sha256
381299f22ca68e82, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).