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BQ25883RGER

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Texas Instruments Battery Management, VQFN-24-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs bq25883rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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bq25883rger-etched.fit.json bq25883rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bq25883rger-etched.glb bq25883rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bq25883rger-etched.step bq25883rger: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
bq25883rger.glb Publish 0.1.0 · Ray 2mo ago
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page.json bq25883rger: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md bq25883rger: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

BQ25883RGER

Texas Instruments · Battery Management · VQFN-24-EP(4x4)

BQ25883RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D- bidirectional Negative USB data line. Used for USB host/charging port detection (BC1.2), including data contact detection (DCD) and secondary detection.
2 STAT output Open drain charge status indicator. Connect to pull-up rail via 10-kΩ resistor. LOW = charge in progress; HIGH = charge complete or disabled; blinks at 1Hz on fault. Can be disabled via STAT_DIS.
3 /CE input Active low charge enable pin. Battery charging is enabled when EN_CHG bit = 1 and /CE pin is LOW. Internally pulled low with 900-kΩ resistor.
4 SDA bidirectional I2C interface data. Connect SDA to the pull-up rail through a 10-kΩ resistor.
5 SCL input I2C interface clock. Connect SCL to the pull-up rail through a 10-kΩ resistor.
6 /INT output Open drain active low interrupt output. Connect to pull-up rail via 10-kΩ resistor. Sends 256-µs active-low pulse to the host to report charger status and fault events.
7 TS input Temperature qualification voltage. Connect a NTC thermistor (recommend 103AT-2). Program temperature window with a resistor divider from REGN to TS to GND; charge suspends when TS is out of range.
8 ILIM input Input current limit (IINDPM) programming. IINDPM loop regulates ILIM pin voltage at 0.8V. Resistor to GND sets IINMAX = KILIM / RILIM. Short to GND for maximum limit; do not float. Cannot set below 500mA.
9 /PG output Open drain active low power good indicator. Connect to pull-up rail via 10-kΩ resistor. LOW indicates a good input source when input voltage is within VVBUS_OP (3.9V) and can provide more than IPOORSRC (30 mA).
10 NC unconnected No connect. Leave floating or tie to ground.
11 REGN power_out Gate drive supply. Bias supply for internal MOSFET drivers and IC. Bypass REGN to GND with a 4.7-µF ceramic capacitor. REGN current limit is 50 mA.
12 BTST power_in PWM high-side driver supply. Internally BTST is connected to the cathode of the boot-strap diode. Connect a 47-nF bootstrap capacitor from SW to BTST.
13 BAT power_in Battery power connection. Connect minimum recommended 10-µF capacitance (after derating) closely to BAT and GND.
14 BAT power_in Battery power connection. Connect minimum recommended 10-µF capacitance (after derating) closely to BAT and GND.
15 SYS power_out System connection. Internal BATFET connects SYS to BAT. When battery falls below minimum system voltage, the switch-mode converter keeps SYS above the minimum. Connect 2x22-µF capacitance (after derating) close to SYS and PGND.
16 SYS power_out System connection. Internal BATFET connects SYS to BAT. When battery falls below minimum system voltage, the switch-mode converter keeps SYS above the minimum. Connect 2x22-µF capacitance (after derating) close to SYS and PGND.
17 SW power_out Inductor connection. Connect to the switched side of the external inductor.
18 SW power_out Inductor connection. Connect to the switched side of the external inductor.
19 GND power_in Ground return.
20 GND power_in Ground return.
21 PMID power_in Blocking MOSFET connection. Total low-ESR capacitance on VBUS and PMID (after derating) is 10 µF; at least 1-µF at VBUS with remainder (typically 10 µF) at PMID.
22 PMID power_in Blocking MOSFET connection. Total low-ESR capacitance on VBUS and PMID (after derating) is 10 µF; at least 1-µF at VBUS with remainder (typically 10 µF) at PMID.
23 VBUS power_in Input supply. VBUS is connected to the external DC supply (3.9-6.2 V operating). Bypass VBUS to GND with at least 1-µF ceramic capacitor placed close to the IC.
24 D+ bidirectional Positive USB data line. Used for USB host/charging port detection (BC1.2), including data contact detection (DCD) and secondary detection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category PMIC
Pins 24

Ordering variants

Same part, different packaging or reel option.

  • BQ25883RGER

CAD (KiCad official)

  • Symbol: BQ25883RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: bq25883rger-etched.step / bq25883rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25883rger.step / bq25883rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (86 pp, sha256 d65790066f0d6360, retrieved 2026-08-17, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF