# BQ25756ERRVR

**Texas Instruments** · Battery Management · VQFN-36-EP(6x5)

BQ25756ERRVR from Texas Instruments, in a VQFN-36-EP(6x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCL | input | I2C interface clock input; connect to the logic rail through a 10 kΩ pull-up resistor. |
| 2 | SDA | bidirectional | I2C interface data line; connect to the logic rail through a 10 kΩ pull-up resistor. |
| 3 | INT | output | Open-drain active-low interrupt output that sends a 256 µs low pulse to the host to report charger status and faults; connect through a 10 kΩ pull-up to the logic rail. |
| 4 | STAT1 | output | Open-drain charge status 1 output (see table 8-6), pulled up through a 10 kΩ resistor; can be disabled with DIS_STAT_PINS and used as a general indicator via FORCE_STAT1_ON. |
| 5 | STAT2 | output | Open-drain charge status 2 output (see table 8-6), pulled up through a 10 kΩ resistor; can be disabled with DIS_STAT_PINS and used as a general indicator via FORCE_STAT2_ON. |
| 6 | PG | output | Open-drain active-low power-good output that goes low when VAC is within the programmed ACUV/ACOV window; pulled up through a 10 kΩ resistor and can be disabled with DIS_PG_PIN. |
| 7 | CE | bidirectional | Active-low charge enable; charging is enabled when EN_CHG is 1 and CE is low, and the pin must be driven high or low and not left floating; can be disabled with DIS_CE_PIN. |
| 8 | TS | input | Battery NTC thermistor voltage input, referenced to REGN with a divider to PGND; charging is suspended when the TS voltage is outside the programmed window, and the recommended thermistor is 103AT-2 10 kΩ. |
| 9 | ICHG | input | Hardware charge current limit setting and monitor pin; a resistor to PGND sets ICHG = KICHG/RICHG, and the pin must be tied to PGND (not floating) if unused. |
| 10 | ILIM_HIZ | input | Input current limit setting, monitor and high-impedance mode control pin; a resistor to PGND sets ILIM = KILIM/RILIM, pulling the pin above VIH_ILIM_HIZ (3.7 V) forces HIZ mode, and the pin must be tied to PGND if unused. |
| 11 | FBG | input | Voltage feedback divider return connected to the bottom of the battery feedback network; driven internally to PGND while charging and high-impedance when the input is outside the ACUV/ACOV window. |
| 12 | FB | input | Analog charge voltage feedback input; the battery-terminal divider output connects here to set the battery regulation voltage (VFB_REG nominal 1.536 V). |
| 13 | SRN | input | Charge current sense resistor negative input; place a 0.47 µF ceramic capacitor between SRN and SRP for differential filtering and an optional 0.1 µF capacitor from SRN to PGND for common-mode filtering. |
| 14 | SRP | input | Charge current sense resistor positive input; place a 0.47 µF ceramic capacitor between SRN and SRP and a 0.1 µF ceramic capacitor from SRP to PGND. |
| 15 | NC | unconnected | No internal connection; leave floating and do not connect to PGND. |
| 16 | NC | unconnected | No internal connection; leave floating and do not connect to PGND. |
| 17 | PGND | power_in | Power ground; connect directly to PGND pin 22. |
| 18 | SW2 | passive | Boost-side half-bridge switch node connected to the boost high-side FET source and boost low-side FET drain; the inductor connects between SW1 and SW2. |
| 19 | HIDRV2 | output | Boost-side high-side gate driver output that drives the gate of the boost high-side N-channel MOSFET. |
| 20 | BTST2 | power_out | Boost-side high-side gate driver bootstrap supply; connect a capacitor between BTST2 and SW2. |
| 21 | LODRV2 | output | Boost-side low-side gate driver output that drives the gate of the boost low-side N-channel MOSFET. |
| 22 | PGND | power_in | Power ground return for the high-current low-side gate drivers. |
| 23 | DRV_SUP | power_in | Charger gate-drive supply input for the switching FETs; place a 4.7 µF ceramic capacitor to ground, and it may be driven directly by an external 4.5 V to 12 V supply (recommended 4.0 V to 12 V) or tied to REGN. |
| 24 | REGN | power_out | Internal linear regulator output (about 5 V) that powers the IC and gate drivers; place a 4.7 µF ceramic capacitor to ground and tie to DRV_SUP for gate drive from REGN. |
| 25 | LODRV1 | output | Buck-side low-side gate driver output that drives the gate of the buck low-side N-channel MOSFET. |
| 26 | BTST1 | power_out | Buck-side high-side gate driver bootstrap supply; connect a capacitor between BTST1 and SW1. |
| 27 | HIDRV1 | output | Buck-side high-side gate driver output that drives the gate of the buck high-side N-channel MOSFET. |
| 28 | SW1 | passive | Buck-side half-bridge switch node connected to the buck high-side FET source and buck low-side FET drain; the inductor connects between SW1 and SW2. |
| 29 | ACN | input | Adapter current sense resistor negative input; place a 0.47 µF ceramic capacitor between ACN and ACP and an optional 0.1 µF capacitor from ACN to PGND. |
| 30 | ACP | input | Adapter current sense resistor positive input; place a 0.47 µF ceramic capacitor between ACN and ACP and a 0.1 µF ceramic capacitor from ACP to PGND. |
| 31 | NC | unconnected | No internal connection; leave floating and do not connect to PGND. |
| 32 | VAC | power_in | Input voltage sense and supply; place a 1 µF capacitor between this pin and PGND, and the pin is regulated to VAC_REV when reverse mode is enabled. |
| 33 | VAC | power_in | Input bias supply for the IC; the ACOV/ACUV resistor divider is connected relative to this pin. |
| 34 | ACUV | input | AC undervoltage comparator input; a resistor divider between VAC and PGND sets the undervoltage threshold (VREF_ACUV 1.1 V), charging stops when the pin is below VREF_ACUV, and the pin must be tied to VAC if unused. |
| 35 | ACOV | input | AC overvoltage comparator input; a resistor divider between VAC and PGND sets the overvoltage threshold (VREF_ACOV 1.2 V), charging stops when the pin rises above VREF_ACOV, and the pin must be tied to PGND if unused. |
| 36 | FSW_SYNC | input | Switching frequency program and external sync input; a resistor to PGND sets the nominal frequency (200 kHz to 600 kHz), and the pin can also accept an external clock of 200 kHz to 600 kHz and must not be left floating. |
| 37 | EP | power_in | Exposed thermal pad under the IC that must be soldered to the board and connected to PGND and the high-current power ground plane through a via star for heat dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-36-EP(6x5) |
| Category | Power Management (PMIC) |
| Pins | 37 |

## CAD (KiCad official)

- Symbol: `BQ25756ERRVR`
- Footprint: `Package_DFN_QFN:QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.6mm`
- 3D model: VQFN-36-EP(6x5) (KiCad packages3D, STEP)
- 3D model files: `bq25756errvr-etched.step` / `bq25756errvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `bq25756errvr.step` / `bq25756errvr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/bq25756e) (83 pp, sha256 `fe3d8029cc4b7d81`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/bq25756errvr-datasheet.pdf)